MOP-TFT320240-35A-BLM-TPC
8
9
AC Characteristics
9.1
Pixel Timing
Figure 3:Pixel Timing
Characteristics
Symbol
Min.
Typ.
Max.
Unit
24 bit
8 bit
24 bit
8 bit
24 bit
8 bit
DOTCLK Frequency
fDOTCLK
-
-
6.5
19.5
10
30
MHz
DOTCLK Period
tDOTCLK
100
33.3
154
51.3
-
-
ns
Vertical Sync Setup Time
tvsys
20
10
-
-
-
-
ns
Vertical Sync Hold Time
tvsyh
20
10
-
-
-
-
ns
Horizontal Sync Setup Time
thsys
20
10
-
-
-
-
ns
Horizontal Sync Hold Time
thsyh
20
10
-
-
-
-
ns
Phase Difference of Sync
Signal Falling Edge
thv
1
-
240
tDOTCLK
DOTCLK Low Period
tCKL
50
15
-
-
-
-
ns
DOTCLK High Period
tCKH
50
15
-
-
-
-
ns
Data Setup Time
tds
12
10
-
-
-
-
ns
Data Hold Time
tdh
12
10
-
-
-
-
ns
Reset pulse width
tRES
10
-
-
μS
*Note: External clock source must be provided to DOTCLK pin of HX8238-D. The driver will not operate if absent of the
clocking signal.
