Marvell Integrated Controller 88F6281 Hardware Specifications Download

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88F6281
Hardware Specifications

Doc. No. MV-S104859-U0 Rev. E

Page 102

Document Classification: Proprietary Information

December 2, 2008, Preliminary

8.6.7.3

JTAG Interface AC Timing Diagrams

Figure 22: JTAG Interface Output Delay AC Timing Diagram

Figure 23: JTAG Interface Input AC Timing Diagram

JTCK

TDO

Tprop

(min)

Tprop

(max)

VIH

VIL

Thold

Tsetup

JTCK

TMS,TDI

Summary of Contents for Integrated Controller 88F6281

Page 1: ...Marvell Moving Forward Faster Doc No MV S104859 U0 Rev E December 2 2008 Preliminary Document Classification Proprietary Information Cover 88F6281 Integrated Controller Hardware Specifications ...

Page 2: ... source code controlled for national security reasons by the U S Export Control Regulations EAR to a national of EAR Country Groups D 1 or E 2 2 Not to export the direct product of such technology or such software to EAR Country Groups D 1 or E 2 if such technology or software and direct products thereof are controlled for national security reasons by the EAR and 3 In the case of technology contro...

Page 3: ...eeva CPU core The CPU core integrates a 256 KB L2 cache Sheeva CPU Core 16 KB I 16 KB D Up to 1 5 GHz AES DES 3DES SHA 1 MD5 Processor Memory Security Engine L2 Cache 256 KB DDR SDRAM Controller JTAG Interface PCI Express SATA USB 2 0 High Speed I 0 PCI Express x1 Dual SATA ports USB 2 0 port 88F6281 Functional Block Diagram External DDR 800 MHz Misc FXS FXO SPI NAND SDIO Slow Bus TDM UART x2 GPIO...

Page 4: ...h Prediction Unit Supports JTAG ARM ICE Supports both Big and Little Endian modes DDR2 SDRAM controller 16 bit interface Up to 400 MHz clock frequency 800 MHz data rate DDR SDRAM with a clock ratio of 1 N and 2 N between the DDR SDRAM and the CPU core respectively SSTL 1 8V I Os Auto calibration of I Os output impedance Supports four DRAM chip selects Supports all DDR devices densities up to 2 Gb ...

Page 5: ...and port Two Integrated Marvell 3 Gbps Gen2i SATA PHYs Compliant with SATA II Phase 1 specifications Supports SATA II Native Command Queuing NCQ up to 128 outstanding commands per port Fully supports first party DMA FPDMA Backwards compatible with SATA I devices Supports SATA II Phase 2 advanced features 3 Gbps Gen2i SATA II speed Port Multiplier PM Performs FIS based switching as defined in SATA ...

Page 6: ...lash interface Glueless interface to CE Care and CE Don t Care NAND flash devices Boot support Serial Peripheral Interface SPI controller Up to 50 MHz clock Supports direct boot from external SPI serial flash memory MPEG Transport Stream TS interface ISO IEC 13818 1 standard compliant Supports any one of the following modes Parallel 8 bit input Parallel output Two independent serial interfaces Dat...

Page 7: ...er 2 2008 Preliminary Document Classification Proprietary Information Page 7 x16 x8 TDM Usage Model Example VoIP Gateway PCI Express Mini Card Wi Fi SD Card USB Host SATA Port Multiplier HDD Audio A D D A GbE PHY FXS FXO NAND Flash SPI Flash op On Board DDR2 88F6281 ...

Page 8: ...3 88F6281 Pin Map and Pin List 50 4 Pin Multiplexing 51 4 1 Multi Purpose Pins Functional Summary 51 4 2 Gigabit Ethernet GbE Pins Multiplexing on MPP 57 4 3 TSMP TS Multiplexing Pins on MPP 59 5 Clocking 60 5 1 Spread Spectrum Clock Generator SSCG 62 6 System Power Up Down and Reset Settings 63 6 1 Power Up Down Sequence Requirements 63 6 2 Hardware Reset 64 6 3 PCI Express Reset 66 6 4 Sheeva CP...

Page 9: ...mum Ratings 75 8 2 Recommended Operating Conditions 77 8 3 Thermal Power Dissipation 79 8 4 Current Consumption 80 8 5 DC Electrical Specifications 81 8 6 AC Electrical Specifications 86 8 7 Differential Interface Electrical Characteristics 118 9 Thermal Data Preliminary 129 10 Package 130 11 Part Order Numbering Package Marking 132 11 1 Part Order Numbering 132 11 2 Package Marking 133 A Revision...

Page 10: ...gnment 37 Table 15 Two Wire Serial Interface TWSI Interface Pin Assignment 38 Table 16 UART Port 0 1 Interface Pin Assignment 39 Table 17 Audio S PDIF I2S Interface Signal Assignment 40 Table 18 Serial Peripheral Interface SPI Interface Signal Assignment 41 Table 19 Secure Digital Input Output SDIO Interface Signal Assignment 42 Table 20 Time Division Multiplexing TDM Interface Signal Assignment 4...

Page 11: ...ing Table at 3 3V 93 Table 51 GMII AC Timing Table 95 Table 52 MII MMII MAC Mode AC Timing Table 97 Table 53 SMI Master Mode AC Timing Table 99 Table 54 JTAG Interface AC Timing Table 101 Table 55 TWSI Master AC Timing Table 103 Table 56 TWSI Slave AC Timing Table 103 Table 57 S PDIF AC Timing Table 105 Table 58 Inter IC Sound I2S AC Timing Table 107 Table 59 TDM Interface AC Timing Table 109 Tabl...

Page 12: ... Page 12 Document Classification Proprietary Information December 2 2008 Preliminary 10 Package 130 Table 73 HSBGA 288 pin Package Dimensions 131 11 Part Order Numbering Package Marking 132 Table 74 88F6281 Part Order Options 132 A Revision History 134 Table 75 Revision History 134 ...

Page 13: ...g Diagram 92 Figure 8 SDRAM DDR2 Interface Read AC Timing Diagram 92 Figure 9 RGMII Test Circuit 94 Figure 10 RGMII AC Timing Diagram 94 Figure 11 GMII Test Circuit 95 Figure 12 GMII Output AC Timing Diagram 96 Figure 13 GMII Input AC Timing Diagram 96 Figure 14 MII MMII MAC Mode Test Circuit 97 Figure 15 MII MMII MAC Mode Output Delay AC Timing Diagram 97 Figure 16 MII MMII MAC Mode Input AC Timi...

Page 14: ...112 Figure 37 Secure Digital Input Output SDIO Test Circuit 113 Figure 38 SDIO Host in High Speed Mode Output AC Timing Diagram 114 Figure 39 SDIO Host in High Speed Mode Input AC Timing Diagram 114 Figure 40 Transport Stream Interface Test Circuit 116 Figure 41 Transport Stream Output Interface AC Timing Diagram 116 Figure 42 Transport Stream Input Interface AC Timing Diagram 117 Figure 43 PCI Ex...

Page 15: ...l Management for Marvell Technology Products Doc No MV S300281 001 AN 179 TWSI Software Guidelines for Discovery Horizon and Feroceon Devices Doc No MV S300754 001 AN 183 88F5181 and 88F5281 Big Endian and Little Endian Support Doc No MV S300767 001 AN 249 Configuring the Marvell SATA PHY to Transmit Predefined Test Patterns Doc No MV S301342 001 AN 260 System Power Saving Methods for 88F6180 88F6...

Page 16: ...r 12 0 Active Low Signals An n letter at the end of a signal name indicates that the signal s active state occurs when voltage is low Example INTn State Names State names are indicated in italic font Example linkfail Register Naming Conventions Register field names are indicated by angle brackets Example RegInit Register field bits are enclosed in brackets Example Field 1 0 Register addresses are ...

Page 17: ...859 U0 Rev E December 2 2008 Preliminary Document Classification Proprietary Information Page 17 1 Pin and Signal Descriptions This section provides the pin logic diagram for the 88F6281 device and a detailed description of the pin assignments and their functionality ...

Page 18: ...TL GE_RXCLK GE_MDC GE_MDIO SDRAM M_CLKOUT M_CLKOUTn M_CKE M_RASn M_CASn M_WEn M_A 14 0 M_BA 2 0 M_CSn 3 0 M_DQ 15 0 M_DQS 1 0 M_DQSn 1 0 M_STARTBURST M_STARTBURST_IN M_PCAL M_NCAL M_DM 1 0 M_ODT 1 0 RTC RTC_XIN RTC_XOUT SATA0 1 SATA0_T_P SATA0_R_P SATA0_R_N SATA0_T_N SATA1_T_P SATA1_T_N SATA1_R_P SATA1_R_N JTAG JT_CLK JT_TDI JT_TDO JT_TMS_CORE JT_RSTn JT_TMS_CPU NAND Flash NF_CLE NF_ALE NF_CEn NF_...

Page 19: ...Represents port number when there are more than one ports Analog Analog Driver Receiver or Power Supply Calib Calibration pad type CML Common Mode Logic CMOS Complementary Metal Oxide Semiconductor DDR Double Data Rate GND Ground Supply HCSL High speed Current Steering Logic I Input I O Input Output O Output o d Open Drain pin The pin allows multiple drivers simultaneously wire OR connection A pul...

Page 20: ...ight 2008 Marvell Page 20 Document Classification Proprietary Information December 2 2008 Preliminary RTC RTC_ NAND Flash NF_ MPP N A TWSI TW_ UART UA0_ UA1_ Audio AU_ SPI SPI_ SDIO SD_ TDM TDM_ PTP PTP_ Table 2 Interface Pin Prefix Codes Continued Interface Prefix ...

Page 21: ...ces VDD_M I Power 1 8V I O supply voltage for the DDR2 SDRAM interface VSS I GND VSS CPU_PLL_AVDD I Power 1 8V analog quiet power to CPU PLL NOTE See the 88F6180 88F6190 88F6192 and 88F6281 Design Guide for power supply filtering recommendations CPU_PLL_AVSS I GND CPU PLL ground CORE_PLL_AVDD I Power 1 8V analog quiet power to Core PLL NOTE See the 88F6180 88F6190 88F6192 and 88F6281 Design Guide ...

Page 22: ...ommendations SATA0_AVDD SATA1_AVDD I Power SATA II port0 1 quiet 3 3V power supply NOTE See 88F6180 88F6190 88F6192 and 88F6281 Design Guide for power supply filtering recommendation USB_AVDD I Power USB 2 0 PHY quiet 3 3V power supply NOTE See the 88F6180 88F6190 88F6192 and 88F6281 Design Guide for power supply filtering recommendation RTC_AVDD I Power 1 5V via battery or 1 8V via the board RTC ...

Page 23: ...in the reset state most output pins are in Tri State SYSRST_OUTn O CMOS VDDO Reset request from the device to the board reset logic This pin is multiplexed on the MPP pins see Section 4 Pin Multiplexing on page 51 PEX_RST_OUTn O CMOS VDDO Optional PCI Express Endpoint card reset output This pin is multiplexed on the MPP pins see Section 4 Pin Multiplexing on page 51 TP O Analog Analog Test Point f...

Page 24: ... M_A 14 0 O SSTL VDD_M SDRAM Address Driven with M_BA 2 0 during RASn and CASn cycles to generate the SDRAM address M_BA 2 0 O SSTL VDD_M Driven during M_RASn and M_CASn cycles to select one of the eight SDRAM virtual banks NOTE If an SDRAM device does not support the BA 2 pin leave the M_BA 2 unconnected M_CSn 3 0 O SSTL VDD_M SDRAM Chip Selects Asserted to select a specific SDRAM Physical bank M...

Page 25: ...6190 88F6192 and 88F6281 Design Guide M_START BURST_IN I SSTL VDD_M Start Burst Input M_PCAL I Calib SDRAM interface P channel output driver calibration Connect to VSS through a resistor The resistor value can vary between 30 70 ohm NOTE See the 88F6180 88F6190 88F6192 and 88F6281 Design Guide for the recommended values of the calibration resistors M_NCAL I Calib SDRAM interface N channel output d...

Page 26: ...ce Clock 100 MHz differential This clock can be configured as input or output according to the reset strap see Table 32 Reset Configuration on page 67 NOTE For Output mode 50 ohm pull down resistors are required PEX_TX_P N O CML PEX_AVDD Transmit Lane Differential pair of PCI Express transmit data PEX_RX_P N I CML PEX_AVDD Receive Lane Differential pair of PCI Express receive data PEX_ISET I Analo...

Page 27: ... 1 SATA0_R_P N SATA1_R_P N I CML SATA0 1_AVDD Receive Data Differential analog input of SATA II port0 1 SATA0_PRESENTn SATA1_PRESENTn O CMOS VDDO VDD_GE_B When this signal is asserted there is an active link between the SATA II port and the external device disk NOTE These signals are multiplexed on the MPP pins see Section 4 Pin Multiplexing on page 51 SATA0_ACTn SATA1_ACTn O CMOS VDDO VDD_GE_B Wh...

Page 28: ...t 2 5 MHz or 25 MHz t s O GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable transmit error and transmit data signals This clock operates at 125 MHz GE_TXD 3 0 t s O CMOS VDD_GE_A RGMII Transmit Data Contains the transmit data nibble outputs that run at double data rate with bits 3 0 driven on the rising edge of GE_TXCLKOUT and bits 7 4 driven on the falling ...

Page 29: ...ock The receive clock provides a 125 MHz 25 MHz or 2 5 MHz reference clock derived from the received data stream MII MMII Receive Clock Provides the timing reference for the reception of the receive data valid receive error and GE_RXD 3 0 signals This clock operates at 2 5 MHz or 25 MHz GMII Receive Clock Provides the timing reference for the reception of the GE_RXDV receive error and receive data...

Page 30: ... reference for the transmission of the MII transmit clock transmit enable and GE_TXD 3 0 signals This clock operates at 2 5 MHz or 25 MHz t s O GMII Transmit Clock Provides the timing reference for the transfer of the transmit enable transmit error and transmit data signals This clock operates at 125 MHz MPP 30 GE1 10 I CMOS VDD_GE_B RGMII Receive Control GE_RXCTL is presented on the rising edge o...

Page 31: ...ous to the GE_TXCLKOUT output rising falling edge GE_TXEN is presented on the rising edge of GE_TXCLKOUT A logical derivative of transmit enable transmit error is presented on the falling edge of GE_TXCLKOUT MII MMII Transmit Error It is synchronous to transmit clock NOTE Multiplexed on MPP GMII Transmit Error It Is synchronous to GE_TXCLKOUT NOTE Multiplexed on MPP MPP 34 GE1 14 O CMOS VDD_GE_B M...

Page 32: ...ble 9 Serial Management Interface SMI Pin Assignments Pin Name I O Pin Type Power Rail Description GE_MDC t s O CMOS VDD_GE_A Management Data Clock MDC is derived from TCLK divided by 128 Provides the timing reference for the transfer of the MDIO signal GE_MDIO t s I O CMOS VDD_GE_A Management Data In Out Used to transfer control and status information between PHY devices and the GbE controller NO...

Page 33: ...59 U0 Rev E December 2 2008 Preliminary Document Classification Proprietary Information Page 33 1 2 8 USB 2 0 Interface Pin Assignments Table 10 USB 2 0 Interface Pin Assignments Pin Name I O Pin Type Power Rail Description USB_DP USB_DM I O CML USB_AVDD USB 2 0 Data Differential Pair ...

Page 34: ... Mode Select Controls CPU JTAG controller state Sampled with the rising edge of JT_CLK NOTE This pin is internally pulled up to 1 JT_TMS_CORE I CMOS VDDO Core JTAG Mode Select Controls the Core JTAG controller state Sampled with the rising edge of JT_CLK NOTE This pin is internally pulled up to 1 JT_TDO O CMOS VDDO JTAG Data Out Driven on the falling edge of JT_CLK JT_TDI I CMOS VDDO JTAG Data In ...

Page 35: ...8 Preliminary Document Classification Proprietary Information Page 35 1 2 10 Real Time Clock RTC Interface Pin Assignments Table 12 RTC Interface Pin Assignments Pin Name I O Pin Type Power Rail Description RTC_XIN I Analog RTC_AVDD RTC Crystal Clock Input RTC_XOUT O Analog RTC_AVDD RTC Crystal Clock Feedback ...

Page 36: ... and data and to input data during read operations NOTE All of the NF_IO pins are multiplexed on the MPP pins see Section 4 Pin Multiplexing on page 51 NF_CLE O CMOS VDDO Command Latch Enable Controls the activating path for commands sent to the command register NF_ALE O CMOS VDDO Address Latch Enable Controls the activating path for the address to the internal address registers NF_CEn O CMOS VDDO...

Page 37: ...signment Table 14 MPP Interface Pin Assignment Pin Name I O Pin Type Power Rail Description MPP 19 0 t s I O CMOS VDDO Multi Purpose Pin Various functionalities MPP 35 20 t s I O CMOS VDD_GE_B Multi Purpose Pin Various functionalities MPP 49 36 t s I O CMOS VDDO Multi Purpose Pin Various functionalities Note The various functionalities of the MPP pins are detailed in Section 4 Pin Multiplexing on ...

Page 38: ...ultiplexing on page 51 Table 15 Two Wire Serial Interface TWSI Interface Pin Assignment Pin Name I O Pin Type Power Rail Description TW_SDA o d I O CMOS VDDO TWSI Port Serial Data Address or write data driven by the TWSI master or read response data driven by the TWSI slave NOTE Requires a pull up resistor to VDDO TW_SCK o d I O CMOS VDDO TWSI Port Serial Clock Serves as output when acting as an T...

Page 39: ... 1 2 14 UART Interface Note All of the UART signals are multiplexed on the MPP pins see Section 4 Pin Multiplexing on page 51 Table 16 UART Port 0 1 Interface Pin Assignment Pin Name I O Pin Type Power Rail Description UA0 1_RXD I CMOS VDDO UART Port 0 1 RX Data UA0 1_TXD O CMOS VDDO UART Port 0 1 TX Data UA0 1_CTS I CMOS VDDO Clear to Send UA0 1_RTS O CMOS VDDO Request to Send ...

Page 40: ...DDO VDD_GE_B S PDIF In AU_SPDIFO O CMOS VDDO VDD_GE_B S PDIF Out AU_ SPDFRMCLK O CMOS VDDO VDD_GE_B S PDIF Recovered Master Clock 256 x Fs 1 For the frequency of this clock see the Audio External Reference Clock section of Table 45 Reference Clock AC Timing Specifications on page 86 AU_I2SBCLK O CMOS VDDO VDD_GE_B I2 S Bit Clock 64 x Fs AU_I2SDO O CMOS VDDO VDD_GE_B Transmitter Data Out AU_I2SLRCL...

Page 41: ...ction 4 Pin Multiplexing on page 51 Table 18 Serial Peripheral Interface SPI Interface Signal Assignment Pin Name I O Pin Type Power Rail Description SPI_MOSI1 O CMOS VDDO SPI Data Output Data is output from the master and input to the slave SPI_MISO2 I CMOS VDDO SPI Data Input Data is input to the master and output from the slave SPI_SCK O CMOS VDDO SPI Clock SPI_CSn O CMOS VDDO SPI Chip Select N...

Page 42: ...ecure Digital Input Output SDIO Interface Signal Assignment Pin Name I O Pin Type Power Rail Description SD_CLK O CMOS VDDO SDIO Clock SD_CMD I O CMOS VDDO SDIO Command Used to transfer a command serially from the SDIO host to the SDIO device Used to transfer a command response serially from the SDIO device to the SDIO host NOTE This pin requires a pull up on board SD_D 3 0 I O CMOS VDDO SDIO Data...

Page 43: ... Channel2 Receive Qualifier TDM_CODEC_ INTn I CMOS VDDO VDD_GE_B Interrupt Signal FROM the SLIC codec TDM_CODEC_ RSTn O CMOS VDDO VDD_GE_B SLIC codec Reset Signal TDM_PCLK I O CMOS VDDO VDD_GE_B PCM Audio Bit Clock TDM_FS I O CMOS VDDO VDD_GE_B TDM Frame Sync Signal TDM_DRX I CMOS VDDO VDD_GE_B PCM Audio Input Data for recording TDM_DTX O CMOS VDDO VDD_GE_B PCM Audio Output Data for playback TDM_S...

Page 44: ...e In a byte the data can be driven MSB or LSB first TDM_SPI_MISO I CMOS VDDO VDD_GE_B Serial SPI read data from the CODEC to the host for register access When TDM_SPI_CS is asserted low this data is driven from CODEC on negative edge of TDM_SPI_SCK It is always driven for eight TDM_SPI_SCK cycles at a time The CODEC drives data on this line only for a read operation when it gets command and addres...

Page 45: ...c byte of the TS packet In serial mode the TS0_SYNC pulse may be active for the entire byte or only for the first bit The polarity is programmable to be either active high or active low TSMP 3 I O CMOS VDDO VDD_GE_B TS0_VAL Port0 Valid Data Indicator When this signal is used and is valid it indicates that valid data is present on TS0_DATA TS0_VAL is active during the TS frame packet data and inact...

Page 46: ...and inactive when there is no TS synchronization In output mode the polarity of TS1_VAL is programmable to be either active high or active low TSMP 9 I O CMOS VDDO VDD_GE_B Parallel Mode TS0_DATA 4 Port0 TS Data bit 4 Serial Mode TS1_ERR Port1 Uncorrectable Packet Error When this signal is used an error indicates that the packet contains an uncorrectable error and therefore should not be used In o...

Page 47: ...e Timing Protocol PTP Interface Note All of the PTP signals are multiplexed on the MPP pins see Section 4 Pin Multiplexing on page 51 Table 22 Precise Timing Protocol PTP Interface Signal Assignment Pin Name I O Pin Type Power Rail Description PTP_CLK I CMOS VDDO PTP Clock PTP_EVENT_REQ I CMOS VDDO Trigger generation to the PTP core PTP_TRIG_GEN O CMOS VDDO Trigger generated by the PTP core ...

Page 48: ...ith a lower value can override this internal resistor Table 23 Internal Pull up and Pull down Pins Pin Name Pin Number Pull up Pull down GE_TXD 0 H02 Pull down GE_TXD 1 H01 Pull down GE_TXD 2 H03 Pull up GE_TXD 3 H04 Pull up GE_TXCTL J04 Pull down GE_MDC L03 Pull up JT_TMS_CORE T14 Pull up JT_RSTn T15 Pull down JT_TDI R14 Pull up JT_TMS_CPU V15 Pull up NF_ALE R10 Pull up NF_REn U11 Pull down NF_CL...

Page 49: ...ted power supply is VDD_GE_B leave it connected to either 3 3V or 1 8V USB Discard the power filter Leave USB_AVDD connected to 3 3V All other signals can be left unconnected PCI Express Discard the analog power filters Leave PEX_AVDD connected to 1 8V Pull down the PEX_CLK_N signal through a 50 kΩ resistor to GND Pull up the PEX_CLK_P signal through a 16 kΩ resistor to 1 8V All other signals can ...

Page 50: ...reliminary 3 88F6281 Pin Map and Pin List The 88F6281 pin list is provided as an Excel file attachment To open the attached Excel pin list file double click the pin icons below 88F6281 Pin Map and Pin List xls Note File attachments are only supported by Adobe Reader 6 0 and above To download the latest version of free Adobe Reader go to http www adobe com ...

Page 51: ...xpress Endpoint card reset output MII MMII GMII RGMII interface signals SATA0 1_ACTn SATA0 1_PRESENTn port 0 and port 1 SATA active and SATA present indications see the SATA section in the 88F6180 88F6190 88F6192 and 88F6281 Functional Specifications NF_IO 7 0 NAND Flash data 7 0 SPI interface SPI_MOSI SPI_MISO SPI_SCK SPI_CSn UART interface port 0 and port 1 Transmit and receive functions UA0_TXD...

Page 52: ...ough the MPP Control register as shown in Table 25 Table 26 lists the functionality of the MPP pins as determined by the MPP Multiplex register see the Pins Multiplexing Interface Registers section in the 88F6180 88F6190 88F6192 and 88F6281 Functional Specifications Table 25 MPP Functionality MPP 19 0 MPP 35 20 MPP 49 36 GPIO GPIO GPIO SATA LEDs SATA LEDs Audio NAND flash GbE TDM TWSI Audio TS UAR...

Page 53: ...MPP 7 GPO 7 out only PEX_RST_ OUTn out SPI_SCn out PTP_TRIG_ GEN out MPP 8 GPIO 8 in out TW_SDA in out UA0_RTS out UA1_RTS out MII0_RXER R in SATA1_PR ESE NTn out PTP_CLK in MII0_COL in MPP 9 GPIO 9 in out TW_SCK in out UA0_CTS in UA1_CTS in SATA0_PR ESE NTn out PTP_EVEN T_REQ in MII0_CRS in MPP 10 GPO 10 out only SPI_SCK out UA0_TXD out SATA1_AC Tn out PTP_TRIG_ GEN out MPP 11 GPIO 11 in out SPI_...

Page 54: ...A0_PR ESENTn out MPP 24 GPIO 24 in out TSMP 4 in out TDM_SPI_ CS0 out GE1 4 AU_I2SDO out MPP 25 GPIO 25 in out TSMP 5 in out TDM_SPI_ SCK out GE1 5 AU_I2SLRC LK out MPP 26 GPIO 26 in out TSMP 6 in out TDM_SPI_ MISO in GE1 6 AU_I2SMC LK out MPP 27 GPIO 27 in out TSMP 7 in out TDM_SPI_ MOSI out GE1 7 AU_I2SDI in MPP 28 GPIO 28 in out TSMP 8 in out TDM_COD EC_INTn in GE1 8 AU_EXTCL K in MPP 29 GPIO 2...

Page 55: ...out TDM_SPI_ CS0 out AU_I2SBCL K out MPP 40 GPIO 40 in out TSMP 4 in out TDM_SPI_ SCK out AU_I2SDO out MPP 41 GPIO 41 in out TSMP 5 in out TDM_SPI_ MISO in AU_I2SLRC LK out MPP 42 GPIO 42 in out TSMP 6 in out TDM_SPI_ MOSI out AU_I2SMC LK out MPP 43 GPIO 43 in out TSMP 7 in out TDM_COD EC_INTn in AU_I2SDI in MPP 44 GPIO 44 in out TSMP 8 in out TDM_COD EC_RSTn out AU_EXTCL K in MPP 45 GPIO 45 in ou...

Page 56: ...Table 32 Reset Configuration on page 67 MPP 8 and MPP 9 wake up as TWSI data and clock pins respectively All other MPP interface pins wake up after reset in 0x0 mode GPIO GPO and are default set to Data Output disabled Tri State Therefore those MPPs that are GPIO are in fact inputs and those that are GPO are Tri State The SPI interface can be configured using one of the following sets of MPP pins ...

Page 57: ...MII0_TXCLK in GE_TXD 3 0 GMII0_TXD 3 0 out RGMII0_TXD 3 0 out RGMII0_TXD 3 0 out MII0_TXD 3 0 out GE_TXCTL GMII0_TXEN out RGMII0_TXCTL out RGMII0_TXCTL out MII0_TXEN out GE_RXD 3 0 GMII0_RXD 3 0 in RGMII0_RXD 3 0 in RGMII0_RXD 3 0 in MII0_RXD 3 0 in GE_RXCTL GMII0_RXDV in RGMII0_RXCTL in RGMII0_RXCTL in MII0_RXDV in GE_RXCLK GMII0_RXCLK in RGMII0_RXCLK in RGMII0_RXCLK in MII0_RXCLK in MPP 8 or MPP...

Page 58: ...in NA NA Table 27 Ethernet Ports Pins Multiplexing Continued Pin Name 1xGMII RGMII0 MII1 MMII1 2xRGMII MII0 MMII0 RGMII1 Note When using Gigabit Ethernet signals on MPPs all relevant Gigabit Ethernet signals except those marked as NA must be implemented For example if using MII and the chosen PHY does not have an MII_RXERR out signal the MII_RX_ERR in MPP 35 must still be configured accordingly an...

Page 59: ... out mode all TS signals are outputs Table 28 summarizes the TS port pins multiplexing Table 28 TS Port Pin Multiplexing Pin Name Functionality in TS serial modes 2x in 2x out in out Functionality in TS parallel in out mode TSMP 0 EXT_CLK in EXT_CLK in TSMP 1 TS0_CLK in out TS0_CLK in out TSMP 2 TS0_SYNC in out TS0_SYNC in out TSMP 3 TS0_VAL in out TS0_VAL in out TSMP 4 TS0_ERR in out TS0_ERR in o...

Page 60: ... 88F6190 88F6192 and 88F6281 Functional Specifications Core PLL Reference clock REF_CLK_XIN 25 MHz Derivative clocks TCLK core clock 200 MHz SDIO Clock 100 MHz Gigabit Ethernet Clock 125 MHz TS unit Clock 100 91 83 77MHz SPI clock TCLK 30 TCLK 4 MHz SMI clock TCLK 128 MHz TWSI clock up to TCLK 1600 NOTE See Table 32 Reset Configuration on page 67 for TCLK frequency configuration NOTE See the TS In...

Page 61: ...0 88F6192 and 88F6281 Functional Specifications PTP Reference clock PTP_CLK 125 MHz The PTP_CLK can be used for the following functions PTP time stamp clock Two options for reference clock PTP_CLK Gigabit Ethernet Clock 125 MHz TS unit clock Two options for reference clock PTP_CLK 2 Core PLL Audio unit clock Two options for reference clock PTP_CLK REF_CLK_XIN 25 MHz For clocking configuration regi...

Page 62: ...spectrum clock for the PLL input See SSCG Disable in Table 32 Reset Configuration on page 67 for SSCG enable bypass configuration settings The SSCG block can be configured to perform up spread down spread and center spread The modulation frequency is configurable Typical frequency is 30 kHz The spread percentage can also be configured up to 1 For additional details see the SSCG Configuration Regis...

Page 63: ... the non core voltages is unimportant so long as the non core voltages power up before the core voltages reach 70 of their voltage level shown in Figure 2 The order of the power up sequence between the core voltages VDD and VDD_CPU is unimportant The reset signal s must be asserted before the core voltages reach 70 of their voltage level shown in Figure 2 The reference clock s inputs must toggle w...

Page 64: ...e powered down before VDD 6 2 Hardware Reset The device has one reset input pin SYSRSTn When asserted the entire chip is placed in its initial state Most outputs are placed in high z except for the following output pins that are still active during SYSRSTn assertion M_CLKOUT M_CLKOUTn M_CKE M_ODT 1 0 M_STARTBURST SYSRST_OUTn Note It is the designer s responsibility to verify that the power sequenc...

Page 65: ...n reset The device includes a power on reset POR circuit for VDD power SYSRST_OUTn is asserted low as long as the MRn input signal is asserted low and for an additional 20 ms after MRn de assertion This is useful for implementations that include a manual reset button 6 2 2 Power On Reset POR The SYSRST_OUTn output signal is asserted low for 20 ms when the power on reset POR circuit is triggered PO...

Page 66: ...is_link_fail_reg_rst field in the PCI Express Debug Control register is cleared the device also resets the PCI Express register file to its default values The device triggers an internal reset if the conf_msk_link_fail field is not masked by PCI Express Debug Control register Both link fail and hot reset conditions trigger a chip internal reset if not masked in the PCI Express interface All the ch...

Page 67: ... useful for board debug purposes and identification of board and system settings for the host software If a signal is pulled up on the board it must be pulled to the proper voltage level Certain reset configuration pins are powered by VDD_GE_A and VDD_GE_B Those pins have multiple voltage options see Table 36 Recommended Operating Conditions on page 77 Table 32 Reset Configuration Pin Configuratio...

Page 68: ...rted combination for CPU_CLK Frequency select CPU_CLK to DDR CLK ratio and CPU_CLK to CPU L2 clock ratio are listed in Table 30 Supported Clock Combinations on page 61 MPP 3 MPP 12 NF_WEn CPU_CLK to CPU L2 Clock Ratio 0x0 Reserved 0x1 2 1 0x2 Reserved 0x3 3 1 0x4 0x7 Reserved NOTE Internally pulled to 0x1 The supported combination for CPU_CLK Frequency select CPU_CLK to DDR CLK ratio and CPU_CLK t...

Page 69: ...88F6281 Functional Specifications For a more detailed description of the boot from SPI flash or NAND flash see the SPI Interface and NAND Flash Interface sections in the 88F6180 88F6190 88F6192 and 88F6281 Functional Specifications There is an option to boot from UART when GE_TXD 2 0 0x2 0x7 For a more detailed description of the boot from UART see the BootROM section in the 88F6180 88F6190 88F619...

Page 70: ...s upon de assertion of SYSRSTn When using Serial ROM Initialization the MPP 9 8 pins must be configured to as TW_SCK MPP 9 and TW_SDA MPP 8 6 6 1 Serial ROM Data Structure Serial ROM data structure consists of a sequence of 32 bit address and 32 bit data pairs as shown in Figure 3 Figure 3 Serial ROM Data Structure MPP 18 Reserved NOTE MUST be externally pulled down to 0x0 during reset Table 32 Re...

Page 71: ... serial ROM starting at offset 0x0 The device assumes 7 bit serial ROM address of b1010000 After receiving the last data identifier default value is 0xFFFFFFFF the device receives an additional byte of dummy data It responds with no ack and then asserts the stop bit The serial EEPROM must contain two address offset bytes It must not be less than a 256 byte ROM 6 7 Boot Sequence The device requires...

Page 72: ...rding to sample at reset setting see Table 32 Reset Configuration on page 67 For bootROM details see the BootROM section in the 88F6180 88F6190 88F6192 and 88F6281 Functional Specifications As part of the CPU boot code the CPU typically performs the following Configures the PCI Express address map Configures the proper SDRAM controller parameters and then triggers SDRAM initialization sets InitEn ...

Page 73: ...ate machine will shift instructions into the Instruction register while in SHIFT IR state and shift data into and from the various data registers when in SHIFT DR state 7 2 Instruction Register The Instruction register IR is a 4 bit two stage register It contains the command that is shifted in when the TAP FSM is in the Shift IR state When the TAP FSM is in the Capture IR state the IR outputs all ...

Page 74: ...egister used to sample and drive all of the device pins during the JTAG tests It is a 2 bit per pin shift register in the device thereby allowing the shift register to sequentially access all of the data pins both for driving and strobing data For further details refer to the BSDL Description file for the device 7 5 ID Register The ID register is a 32 bit deep serial shift register The ID register...

Page 75: ... CORE_PLL_AVDD 0 5 2 2 V Analog supply for the internal PLL SSCG_AVDD 0 5 2 2 V Analog supply for Internal Spread Spectrum Clock Generator VDD_GE_A VDD_GE_B 0 5 4 0 V I O voltage for RGMII GMII MII MMII SMI interface VDD_M 0 5 2 2 V I O voltage for SDRAM interface VDDO 0 5 4 0 V I O voltage for MPP TWSI JTAG SDIO I2 S SPI TS and TDM interfaces VHV 0 5 3 0 V I O voltage for eFuse burning PEX_AVDD 0...

Page 76: ...AVDD 0 5 2 2 V Analog supply for RTC interface TC 40 125 C Case temperature TSTG 40 125 C Storage temperature Table 35 Absolute Maximum Ratings Continued Parameter Min Max Units Comments Caution Exposure to conditions at or beyond the maximum rating may damage the device Operation beyond the recommended operating conditions Table 36 is neither recommended nor guaranteed ...

Page 77: ...ly GMII MII MMII SMI interfaces 1 7 1 8 1 9 V I O voltage for RGMII SMI interfaces VDD_M 1 7 1 8 1 9 V I O voltage for SDRAM interface VDDO 3 15 3 3 3 45 V I O voltage for MPP TWSI JTAG SDIO I2 S SPI TS and TDM interfaces VHV during eFuse Burning mode 2 375 2 5 2 625 V I O voltage for eFuse burning NOTE If the VHV voltage is higher than VDD voltage burning mode VDD must be powered before VHV to pr...

Page 78: ... clock inverter for crystal support and current source for SATA and USB PHYs RTC_AVDD 1 7 1 8 1 9 V Analog supply for RTC in Regular mode 1 3 1 5 1 7 V Analog supply for RTC in Battery Back up mode TJ 0 105 C Junction Temperature Table 36 Recommended Operating Conditions Continued Parameter Min Typ Max Units Comments Caution Operation beyond the recommended operating conditions is neither recommen...

Page 79: ...ptimal operating conditions for Marvell Technology s products Table 37 Thermal Power Dissipation Interface Symbol Test Conditions Typ Units Core VDD 1 0V PVDD TCLK 200 MHz 280 mW Embedded CPU VDD_CPU 1 1V PVDD_CPU CPU 1000 MHz L2 333 MHz 790 mW CPU 1200 MHz L2 400 MHz 870 mW CPU 1500 MHz L2 500 MHz 1050 mW RGMII 1 8V interface PRGMII 30 mW RGMII 10 100 RGMII only 3 3V interface PRGMII 50 mW GMII 3...

Page 80: ...Current Consumption Interface Symbol Test Conditions Max Units Core VDD 1 0V IVDD TCLK 200 MHz 600 mA Embedded CPU VDD_CPU 1 1V IVDD_CPU CPU 1000 MHz L2 333 MHz 1920 mA CPU 1200 MHz L2 400 MHz 2010 mA CPU 1500 MHz L2 500 MHz 2100 mA RGMII 1 8V or 3 3V interface IRGMII 25 mA GMII 3 3V interface IGMII 25 mA MII MMII 3 3V interface IMII_MMII 25 mA Miscellaneous interfaces JTAG TWSI UART NAND flash Au...

Page 81: ...TP and MPP interfaces VDDIO means the VDDO power rail For the RGMII GMII MII MMII interface VDDIO means the VDD_GE_A and VDD_GE_B power rails Table 39 General 3 3V Interface CMOS DC Electrical Specifications Note See Section 1 3 Internal Pull up and Pull down Pins on page 48 for internal pullup pulldown information Parameter Symbol Test Condition Min Typ Max Units Notes Input low level VIL 0 3 0 8...

Page 82: ...he XTAL_AVDD power rail Table 40 RGMII 1 8V Interface CMOS DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Units Notes Input low level VIL 0 3 0 35 VDDIO V Input high level VIH 0 65 VDDIO VDDIO 0 3 V Output low level VOL IOL 2 mA 0 45 V Output high level VOH IOH 2 mA VDDIO 0 45 V Input leakage current IIL 0 VIN VDDIO 10 10 uA 1 2 Pin capacitance Cpin 5 pF Notes General com...

Page 83: ...4 mA 1 42 V 120 150 180 ohm 1 2 60 75 90 ohm 1 2 40 50 60 ohm 1 2 Deviation of VMw ith respect to VDDQ 2 dVm See note 3 6 6 3 Input leakage current IIL 0 VIN VDDIO 10 10 uA 4 5 Pin capacitance Cpin 5 pF Notes General comment See the Pin Description section for internal pullup pulldow n 1 See SDRAMfunctional description section for ODT configuration 2 Measurement definition for RTT Apply VREF 0 25 ...

Page 84: ...h level VIH 0 7 VDDIO VDDIO 0 5 V Output low level VOL IOL 3 mA 0 4 V Input leakage current IIL 0 VIN VDDIO 10 10 uA 1 2 Pin capacitance Cpin 5 pF Notes General comment See the Pin Description section for internal pullup pulldow n 1 While I O is in High Z 2 This current does not include the current flow ing through the pullup pulldow n resistor Parameter Symbol Test Condition Min Typ Max Units Not...

Page 85: ...nfigured for the TDM interface Table 44 TDM Interface 3 3V DC Electrical Specifications Parameter Symbol Test Condition Min Typ Max Units Notes Input low level VIL 0 5 0 3 VDDIO V Input high level VIH 0 7 VDDIO VDDIO 0 5 V Output low level VOL IOL 4 mA 0 4 V Output high level VOH IOH 4 mA VDDIO 0 6 V Input leakage current IIL 0 VIN VDDIO 10 10 uA 1 2 Pin capacitance Cpin 5 pF Notes General comment...

Page 86: ...ode clock duty cycle DCGE_TXCLK_OUT 35 65 7 DCGE_RXCLK Slew rate SRGE_TXCLK_OUT 0 7 V ns 1 7 SRGE_RXCLK Audio External Reference Clock Audio external reference clock FAU_EXTCLK 256 X Fs kHz 3 S PDIF Recovered Master Clock S PDIF recovered master clock FAU_SPDFRMCLK 256 X Fs kHz 3 I2 S Reference Clock I2 S clock FI2S_BCLK 64 X Fs kHz 3 SPI Output Clock SPI output clock FSPI_SCK TCLK 30 TCLK 4 MHz 2...

Page 87: ...s recommended by the crystal manufacturer 5 The frequency can be set using the TS Interface Configuration register see the 88F6180 88F6190 88F6192 and 88F6281 Functional Specifications 6 For the minimum value refer to the Baud Rate Register section of the 88F6180 88F6190 88F6192 and 88F6281 Functional Specifications 7 The Ethernet Reference Clock parameters refer both to the reference clock for an...

Page 88: ...el w idth tCL avg 0 48 0 52 tCK avg 1 2 4 DQ input setup time relative to DQS in transition tDSI 0 42 ns DQ input hold time relative to DQS in transition tDHI 0 70 ns Address and control output pulse w idth tIPW 0 60 tCK avg Notes General comment All timing values are defined from Vref to Vref unless otherw ise specified General comment All input timing values assume minimum slew rate of 1 V ns sl...

Page 89: ...5 ns 1 3 Address and Control valid output time after CLK CLKn rising edge tAOVA 0 65 ns 1 3 Notes General comment All timing values w ere measured from vref to vref unless otherw ise specified General comment For all signals the load is CL 14 pF 1 This timing value is defined on CLK CLKn crossing point 2 This timing value is defined w hen Address and Control signals are output on CLK CLKn falling ...

Page 90: ...the largest deviation of any single tCK from tCK avg tJIT per Min max of tCKi tCK avg w here i 1 to 200 tJIT per defines the single period jitter w hen the DLL is already locked 2 tJIT per lck uses the same definition for single period jitter during the DLL locking period only 3 tJIT cc is defined as the difference in clock period betw een tw o consecutive clock cycles tJIT cc Max of tCKi 1 tCKi t...

Page 91: ...t Classification Proprietary Information Page 91 8 6 2 3 SDRAM DDR2 Interface Test Circuit Figure 5 SDRAM DDR2 Interface Test Circuit 8 6 2 4 SDRAM DDR2 Interface AC Timing Diagrams Figure 6 SDRAM DDR2 Interface Write AC Timing Diagram CL 50 ohm VTT Test Point tDSS tDSH DQS tWPRE tDQSH tDQSL tWPST DQ tDIPW tDOVB tDOVA CLKn CLK tCL tCH DQSn ...

Page 92: ...ell Page 92 Document Classification Proprietary Information December 2 2008 Preliminary Figure 7 SDRAM DDR2 Interface Address and Control AC Timing Diagram Figure 8 SDRAM DDR2 Interface Read AC Timing Diagram ADDRESS CONTROL tIPW tAOVB tAOVA CLKn CLK tCL tCH tDHI tDSI DQ DQS DQSn ...

Page 93: ... an additional trace delay of greater than 1 5 ns and less than 2 0 ns is added to the associated clock signal For 10 100 Mbps RGMII the Max value is unspecified 1 For RGMII at 10 Mbps and 100 Mbps Tcyc w ill scale to 400 ns 40 ns and 40 ns 4 ns respectively 2 For all signals the load is CL 5 pF 125 0 Description Symbol Min Max Units Notes Clock frequency fCK MHz Data to Clock output skew Tskew T ...

Page 94: ...94 Document Classification Proprietary Information December 2 2008 Preliminary 8 6 3 2 RGMII Test Circuit Figure 9 RGMII Test Circuit 8 6 3 3 RGMII AC Timing Diagram Figure 10 RGMII AC Timing Diagram CL Test Point At Transmitter TX DATA TX CLOCK RX DATA RX CLOCK At Receiver TskewT TskewR ...

Page 95: ...H 2 5 ns 1 GTX_CLK and RX_CLK low level w idth tLOW 2 5 ns 1 GTX_CLK and RX_CLK rise time tR 1 0 ns 1 2 GTX_CLK and RX_CLK fall time tF 1 0 ns 1 2 Data input setup time relative to RX_CLK rising edge tSETUP 2 0 ns Data input hold time relative to RX_CLK rising edge tHOLD 0 0 ns Data output valid before GTX_CLK rising edge tOVB 2 5 ns 1 Data output valid after GTX_CLK rising edge tOVA 0 5 ns 1 Note...

Page 96: ...roprietary Information December 2 2008 Preliminary 8 6 4 3 GMII AC Timing Diagrams Figure 12 GMII Output AC Timing Diagram Figure 13 GMII Input AC Timing Diagram GTX_CLK TXD TX_EN TX_ER VIH min VIL max VIH min VIL max tOVB tLOW tHIGH tOVA VIH min VIL max VIH min VIL max tSETUP RX_CLK RXD RX_EN RX_ER tHOLD tLOW tHIGH ...

Page 97: ... Circuit Figure 14 MII MMII MAC Mode Test Circuit 8 6 5 3 MII MMII MAC Mode AC Timing Diagrams Figure 15 MII MMII MAC Mode Output Delay AC Timing Diagram Description Symbol Min Max Units Notes Data input setup relative to RX_CLK rising edge tSU 3 5 ns Data input hold relative to RX_CLK rising edge tHD 2 0 ns Data output delay relative to MII_TX_CLK rising edge tOV 0 0 10 0 ns 1 Notes General comme...

Page 98: ... No MV S104859 U0 Rev E Copyright 2008 Marvell Page 98 Document Classification Proprietary Information December 2 2008 Preliminary Figure 16 MII MMII MAC Mode Input AC Timing Diagram tHD Vih min Vih min Vil max tSU RX_CLK RXD RX_EN RX_ER ...

Page 99: ...Max Units Notes MDC clock frequency fCK MHz 2 MDC clock duty cycle tDC 0 4 0 6 tCK MDIO input setup time relative to MDC rise time tSU 40 0 ns MDIO input hold time relative to MDC rise time tHO 0 0 ns MDIO output valid before MDC rise time tOVB 15 0 ns 1 MDIO output valid after MDC rise time tOVA 15 0 ns 1 Notes General comment All timing values w ere measured from VIL max and VIH min levels unles...

Page 100: ...y Information December 2 2008 Preliminary Figure 18 MDC Master Mode Test Circuit 8 6 6 3 SMI Master Mode AC Timing Diagrams Figure 19 SMI Master Mode Output AC Timing Diagram Figure 20 SMI Master Mode Input AC Timing Diagram CL Test Point MDC MDC MDIO VIH min VIH min VIL max tOVA tOVB MDC MDIO VIH min VIH min VIL max tSU tHO ...

Page 101: ...Hz JTClk minimum pulse w idth Tpw 0 45 0 55 tCK JTClk rise fall slew rate Sr Sf 0 50 V ns 2 JTRSTn active time Trst 1 0 ms TMS TDI input setup relative to JTClk rising edge Tsetup 6 67 ns TMS TDI input hold relative to JTClk rising edge Thold 13 0 ns JTClk falling edge to TDO output delay Tprop 1 0 8 33 ns 1 Notes General comment All values w ere measured from vddio 2 to vddio 2 unless otherw ise ...

Page 102: ...102 Document Classification Proprietary Information December 2 2008 Preliminary 8 6 7 3 JTAG Interface AC Timing Diagrams Figure 22 JTAG Interface Output Delay AC Timing Diagram Figure 23 JTAG Interface Input AC Timing Diagram JTCK TDO Tprop min Tprop max VIH VIL Thold Tsetup JTCK TMS TDI ...

Page 103: ... values referred to VIH min and VIL max levels unless otherw ise specified General comment tCK 1 fCK 1 See Reference Clocks table for more details 2 For all signals the load is CL 100 pF and RL value can be 500 ohm to 8 kilohm 3 Rise time measured from VIL max to VIH min fall time measured from VIH min to VIL max See note 1 Min Max SCK minimum low level w idth tLOW 4 7 us 1 SCK minimum high level ...

Page 104: ...ember 2 2008 Preliminary 8 6 8 2 TWSI Test Circuit Figure 24 TWSI Test Circuit 8 6 8 3 TWSI AC Timing Diagrams Figure 25 TWSI Output Delay AC Timing Diagram Figure 26 TWSI Input AC Timing Diagram CL RL VDDIO Test Point SCK SDA Vih min Vil max Vih min Vil max tHIGH tLOW tOV max tOV min Vih min Vil max Vih min Vil max tSU tLOW tHIGH SCK SDA tHD ...

Page 105: ...2 Jitter transfer gain Txjitgain 3 0 dB 3 10 0 UI 4 0 25 UI 5 0 2 UI 6 Notes General comment All values w ere measured from VIL max to VIH min unless otherw ise specified General comment For more information refer to the Digital Audio Interface Part 3 Consumer Applications IEC 60958 3 2003 E Chapter 7 3 January 2003 1 For all signals the load is CL 10 pF 2 Using inristic jitter filter 3 Refer to F...

Page 106: ...pecifications Doc No MV S104859 U0 Rev E Copyright 2008 Marvell Page 106 Document Classification Proprietary Information December 2 2008 Preliminary 8 6 9 2 S PDIF Test Circuit Figure 27 S PDIF Test Circuit CL Test Point ...

Page 107: ... Circuit Description Symbol Min Max Units Notes I2SBCLK clock frequency fCK MHz 2 I2SBCLK clock high low level pulse w idth tCH tCL 0 37 tCK 1 I2SDI input setup time relative to I2SBCLK rise time tSU 0 10 tCK I2SDI input hold time relative to I2SBCLK rise time tHO 0 00 ns I2SDO I2SLRCLK output delay relative to I2SBCLK rise time tOD 0 10 0 70 tCK 1 Notes General comment All timing values w ere mea...

Page 108: ...ation December 2 2008 Preliminary 8 6 10 3 Inter IC Sound I2S AC Timing Diagrams Figure 29 Inter IC Sound I2 S Output Delay AC Timing Diagram Figure 30 Inter IC Sound I2 S Input AC Timing Diagram I2SBCLK I2SDO I2SLRCLK VIH min VIH min VIL max tODmin tODmax VIL max tCH tCL I2SDI VIH min VIL max tSU tHO I2SBCLK VIH min VIL max tCH tCL ...

Page 109: ...ime relative to PCLK falling edge tSU 10 0 ns 5 7 DRX and FSYNC hold time relative to PCLK falling edge tHD 10 0 ns 5 7 Notes General comment All values w ere measured from vddio 2 to vddio 2 unless otherw ise specified 1 For all signals the load is CL 20 pF 2 Rise and Fall times are referenced to the 20 and 80 levels of the w aveform 3 PCLK can be configured to 0 256 0 512 0 768 1 024 1 536 2 048...

Page 110: ...arvell Page 110 Document Classification Proprietary Information December 2 2008 Preliminary 8 6 11 3 TDM Interface Timing Diagrams Figure 32 TDM Interface Output Delay AC Timing Diagram Figure 33 TDM Interface Input Delay AC Timing Diagram tD PCLK DTX tC tD tSU PCLK DRX tC tHD ...

Page 111: ...46 tCK 1 SCLK low time tCL 0 46 tCK 1 SCLK slew rate tSR 0 5 V ns 1 Data out valid relative to SCLK falling edge tDOV 2 5 2 5 ns 1 CS active before SCLK rising edge tCSB 8 0 ns 1 CS not active after SCLK rising edge tCSA 8 0 ns 1 Data in setup time relative to SCLK rising edge tSU 0 2 tCK 2 Data in hold time relative to SCLK rising edge tHD 5 0 ns 2 Notes General comment All values w ere measured ...

Page 112: ...2 Document Classification Proprietary Information December 2 2008 Preliminary 8 6 12 3 SPI Master Mode Timing Diagrams Figure 35 SPI Master Mode Output AC Timing Diagram Figure 36 SPI Master Mode Input AC Timing Diagram SCLK tCL tCH Data Out CS tDOVmax tDOVmin tCSB tCSA tSU SCLK Data in tHD ...

Page 113: ... Test Circuit Description Symbol Min Max Units Notes Clock frequency in Data Transfer Mode fCK 0 50 MHz Clock high low level pulse width tWL tWH 0 35 tCK 1 3 Clock rise fall time tTLH tTHL 3 0 ns 1 3 CMD DAT output valid before CLK rising edge tDOVB 6 5 ns 2 3 CMD DAT output valid after CLK rising edge tDOVA 2 5 ns 2 3 CMD DAT input setup relative to CLK rising edge tISU 7 0 ns 2 CMD DAT input hol...

Page 114: ... 2 2008 Preliminary 8 6 13 3 Secure Digital Input Output SDIO AC Timing Diagrams Figure 38 SDIO Host in High Speed Mode Output AC Timing Diagram Figure 39 SDIO Host in High Speed Mode Input AC Timing Diagram DAT CMD VIH min VIL max CLK VIH min VIL max tWH tWL tDOVB tDOVA VDDIO 2 DAT CMD VIH min VIL max CLK VIH min VIL max tWH tWL tISU tIHD VDDIO 2 ...

Page 115: ...ll values w ere measured from VIL max to VIH min unless otherw ise specified General comment tCK 1 fCK 1 See Reference Clocks table for more details 2 For all signals the load is CL 5 pF 3 When configured to falling edge the tOV parameter is relative to Clock falling edge See note 1 Description Symbol Min Max Units Notes Clock frequency fCK MHz 1 Clock minimum low level w idth tLOW 0 35 0 65 tCK C...

Page 116: ...ation December 2 2008 Preliminary 8 6 14 2 Transport Stream Interface Test Circuit Figure 40 Transport Stream Interface Test Circuit 8 6 14 3 Transport Stream Interface Timing Diagrams Figure 41 Transport Stream Output Interface AC Timing Diagram CL Test Point tOV min Clock Data Out Vih min Vil max Vih min Vil max tOV max tHIGH tLOW ...

Page 117: ...pyright 2008 Marvell Doc No MV S104859 U0 Rev E December 2 2008 Preliminary Document Classification Proprietary Information Page 117 Figure 42 Transport Stream Input Interface AC Timing Diagram Vih min Vil max Vih min Vil max tSU tLOW tHIGH Clock Data In tHD ...

Page 118: ...Units Notes Clock frequency fCK MHz Clock duty cycle DCrefclk 0 4 0 6 tCK Differential rising falling slew rate SRrefclk 0 6 4 0 V nS 3 Differential high voltage VIHrefclk 150 0 mV Differential low voltage VILrefclk 150 0 mV Absolute crossing point voltage Vcross 250 0 550 0 mV 1 Variation of Vcross over all rising clock edges Vcrs_dlta 140 0 mV 1 Average differential clock period accuracy Tperavg...

Page 119: ... 2 2008 Preliminary Document Classification Proprietary Information Page 119 PCI Express Interface Spread Spectrum Requirements Table 65 PCI Express Interface Spread Spectrum Requirements Symbol Min Max Units Notes Fmod 0 0 33 0 kHz 1 Fspread 0 5 0 0 1 Notes 1 Defined on linear sw eep or Hershey s Kiss US Patent 5 631 920 modulations ...

Page 120: ...ltage VTXpp 0 8 1 2 V Minimum TX eye w idth TTXeye 0 75 UI Differential return loss TRLdiff 10 0 dB 1 Common mode return loss TRLcm 6 0 dB 1 DC differential TX impedance ZTXdiff 80 0 120 0 Ohm Differential input peak to peak voltage VRXpp 0 175 1 2 V Minimum receiver eye w idth TRXeye 0 4 UI Differential return loss RRLdiff 10 0 dB 1 Common mode return loss RRLcm 6 0 dB 1 DC differential RX impeda...

Page 121: ...e 121 8 7 2 2 PCI Express Interface Test Circuit Figure 43 PCI Express Interface Test Circuit When measuring Transmitter output parameters C_TX is an optional portion of the Test Measurement load When used the value of C_TX must be in the range of 75 nF to 200 nF C_TX must not be used when the Test Measurement load is placed in the Receiver package reference plane Test Points C_TX 50 ohm 50 ohm C_...

Page 122: ...Page 122 Document Classification Proprietary Information December 2 2008 Preliminary 8 7 3 SATA Interface Electrical Characteristics The driver and receiver characteristics for the SATA I Interface Gen1i Mode and the SATA II Interface Gen2i Mode are provided in the following sections ...

Page 123: ...UI TJ250 0 470 UI 1 Deterministic jitter at connector data data 250UI DJ250 0 220 UI Differential impedance Zdiffrx 85 0 115 0 Ohm Single ended impedance Zsetx 40 0 Ohm Differential return loss 75 MHz 150 MHz RLID 18 0 dB Differential return loss 150 MHz 300 MHz RLID 14 0 dB Differential return loss 300 MHz 600 MHz RLID 10 0 dB Differential return loss 600 MHz 1 2 GHz RLID 8 0 dB Differential retu...

Page 124: ... 0 19 UI 4 Input differential voltage Vdiffrx 275 0 750 0 mV 5 Differential return loss 150 MHz 300 MHz RLID 18 0 dB Differential return loss 300 MHz 600 MHz RLID 14 0 dB Differential return loss 600 MHz 1 2 GHz RLID 10 0 dB Differential return loss 1 2 GHz 2 4 GHz RLID 8 0 dB Differential return loss 2 4 GHz 3 0 GHz RLID 3 0 dB Differential return loss 3 0 GHz 5 0 GHz RLID 1 0 dB Total jitter at ...

Page 125: ...tal for paired transitions TUDJ2 150 0 150 0 ns 5 Input single ended high VIH 2 0 V Input single ended low VIL 0 8 V Differential input sensitivity VDI 0 2 V Notes General Comment For more information refer to Universal Serial Bus Specification Revision 2 0 April 2000 General Comment The load is 100 ohm differential for these parameters unless otherw ise specified General Comment To comply w ith t...

Page 126: ...IL 0 8 V Differential input sensitivity VDI 0 2 V Receiver jitter to next transition tJR1 18 5 18 5 ns 6 Receiver jitter for paired transitions tJR2 9 0 9 0 ns 6 Notes General Comment For more information refer to Universal Serial Bus Specification Revision 2 0 April 2000 General Comment The load is 100 ohm differential for these parameters unless otherw ise specified General Comment To comply w i...

Page 127: ...s 3 Data signaling common mode voltage range VHSCM 50 0 500 0 mV Receiver jitter tolerance 3 Notes General Comment For more information refer to Universal Serial Bus Specification Revision 2 0 April 2000 General Comment The load is 100 ohm differential for these parameters unless otherw ise specified General Comment To comply w ith the values presented in this table refer to your local Marvell rep...

Page 128: ... Preliminary Figure 45 High Speed TX Eye Diagram Pattern Template Figure 46 High Speed RX Eye Diagram Pattern Template 400mV Differential 400mV Differential 0 Volts Differential 0 100 525mV 475mV 475mV 525mV 7 5 92 5 300mV 300mV 37 5 62 5 400mV Differential 400mV Differential 0 Volts Differential 0 100 525mV 475mV 475mV 525mV 12 5 87 5 175mV 175mV 35 65 ...

Page 129: ...ents Application Note AN 63 Thermal Management for Selected Marvell Products Document Number MV S300281 00 White Paper ThetaJC ThetaJA and Temperature Calculations Document Number MV S700019 00 Note TET The thermal parameters are preliminary and subject to change Table 72 Thermal Data for the 88F6281 in the BGA 19 x 19 mm Package Preliminary Symbol Definition Airflow Value C W 0 m s 1 m s 2 m s θJ...

Page 130: ...04859 U0 Rev E Copyright 2008 Marvell Page 130 Document Classification Proprietary Information December 2 2008 Preliminary 10 Package This section provides the 88F6281 package drawing and dimensions Figure 47 HSBGA 288 pin Package and Dimensions ...

Page 131: ...ld thickness A3 0 850 ref Substrate thickness A2 0 560 ref Ball diameter 0 600 Standoff A1 0 400 0 600 Ball width b 0 500 0 700 Mold area X M 17 000 Y N 17 000 H S exposed size P 12 000 13 200 H S flatness Q 0 100 H S shift with substrate edge R 0 300 H S shift with mold area S 0 500 Chamfer CA 1 215 ref Package edge tolerance aaa 0 200 Substrate flatness bbb 0 250 Mold flatness ccc 0 350 Copolari...

Page 132: ...arts r Figure 48 Sample Part Number xx BIA2Cxxx xxxx Part number 88F6281 Package code BIA 288 pin HSBGA Environmental code 2 Green RoHS 6 6 and Halogen free Temperature code C Commercial I Industrial Die revision Custom code optional 88F6281 Speed code 100 1 0 GHz 120 1 2 GHz 150 1 5 GHz Custom code Table 74 88F6281 Part Order Options Package Type Part Order Number 288 pin BGA 88F6281 xx BIA2C100 ...

Page 133: ...XXXX Marvell logo Date code custom code assembly plant code YYWW Date code YY year WW Work Week xx Custom code Assembly plant code Country of origin code Contained in the mold ID or marked as the last line on the package Part number prefix package code environmental code 88F6 Part number prefix BIA Package code e Environmental code 2 Green Note The above drawing is not drawn to scale Location of m...

Page 134: ...ls must be implemented 8 In the Table 32 Reset Configuration on page 67 revised the configuration function for parameter CPU_CLK to DDR CLK Ratio 9 In Table 36 Recommended Operating Conditions on page 77 for parameter RTC_AVDD Analog supply for RTC in Battery Back up mode revised the values for the minimum to 1 3V from 1 4V and for the maximum to 1 7V from 1 6V 10 In Table 37 Thermal Power Dissipa...

Page 135: ...ed the description of VDD_GE_A and VDD_GE_B to add additional information about RGMII 6 In Table 4 Miscellaneous Pin Assignments on page 23 added the signal MRn 7 In Table 5 DDR SDRAM Interface Pin Assignments on page 24 revised the description of M_NCASL and M_PCAL to indicate the range of the resistor 8 In Table 6 PCI Express Interface Pin Assignments on page 26 changed PEX_CLK_P N for input to ...

Page 136: ...vised Table 45 Reference Clock AC Timing Specifications on page 86 30 In Table 34 IDCODE Register Map on page 74 revised the description of bits 31 28 31 In Table 35 Absolute Maximum Ratings on page 75 Added VHV Revised the voltage for the SATA and XTAL AVDD parameters 32 In the Table 36 Recommended Operating Conditions on page 77 Added values for VDD_CPU Added VHV and revised the voltage for the ...

Page 137: ...to Requires a pull up resistor to VDDO 10 Added Section 2 Unused Interface Strapping on page 49 11 In Table 29 88F6281Clocks on page 60 revised the description of CPU PLL to mention SSCG 12 Added Section 5 1 Spread Spectrum Clock Generator SSCG on page 62 13 Added Section 6 1 Power Up Down Sequence Requirements on page 63 and revised the title of Section 6 to reflect this change 14 In Section 6 4 ...

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Page 140: ...Marvell Moving Forward Faster Marvell Semiconductor Inc 5488 Marvell Lane Santa Clara CA 95054 USA Tel 1 408 222 2500 Fax 1 408 752 9028 www marvell com Contact INFORMATION ...

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