Marantz SR6006/K1B, Service Manual

Page: 186 / 225

186
LAN8700 (HDMI : IC322)
LAN8700 Block Diagram
nINT/TX_ER/TXD4
MDC
CRS/PHYAD4
MDIO
nRST
TX_EN
VDD_CORE
VDD33
LI
N
K
/P
H
YA
D1
A
C
TI
V
IT
Y
/P
H
YA
D2
FD
U
PL
EX
/P
H
YA
D3
XT
AL
2
C
LK
IN
/X
TA
L1
R
XD
3/nI
N
TS
EL
R
XD
1/
M
OD
E1
R
XD
2/
M
OD
E2
TXD3
RX_CLK/REGOFF
TX_CLK
RX_ER/RXD4
VDDIO
TXD1
TXD0
TXD2
C
O
L/
R
M
II/
C
R
S
_D
V
TX
P
R
XN
V
D
D
A3.3
E
XR
ES
1
V
D
D
A3.3
R
XP
V
D
D
A3.3
USB3300
Hi-Speed USB2
ULPI PHY
32 Pin QFN
1
2
3
4
5
6
7
8
LAN8700/LAN8700I
MII/RMII Ethernet PHY
36 Pin QFN
GND FLAG
10 11 12 13 14 15 16
24
23
22
21
20
19
32 31 30 29 28
SPEED100/PHYAD0 V D _ X R 9
R
XD
0/
M
OD
E0
17
TX
N
18
27
26
25
36 35 34 33
10M Rx
Logic
100M Rx
Logic
DSP System:
Clock
Data Recovery
Equalizer
Analog-to-
Digital
100M PLL
Squelch &
Filters
10M PLL
Receive Section
Central
Bias
HP Auto-MDIX
Management
Control
SMI
R
M
II /
M
II L
og
ic
TXP / TXN
TXD[0..3]
TX_EN
TX_ER
TX_CLK
RXD[0..3]
RX_DV
RX_ER
RX_CLK
CRS
COL/CRS_DV
MDC
MDIO
SPEED100
LINK
ACTIVITY
FDUPLEX
LED Circuitry
MODE Control
nINT
nRST RXP / RXN
10M Tx
Logic
10M
Transmitter
100M Tx
Logic
100M
Transmitter
Transmit Section
PLL
XTAL1
XTAL2
MODE0
MODE1
MODE2
PHY
Address
Latches
PHYAD[0..4]
Auto-
Negotiation
Interrupt
Generator
MII
MDIX
Control