Marantz SR5000, Service Manual

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VDD1
RAMCEN
RAMA16 RAMA15
SDIB0 SDIB1 SDIB2
XI
XO
VSS
A
VDD
SDIB3
TEST TEST A
VSS
VDD2
SDO
A2
SDO
A1
SDO
A0
RAMA14 RAMA13 RAMA12 RAMA11 RAMA10
VSS
VDD1
OPORT0
OPORT1
OPORT2
OPORT3
OPORT4
OPORT5
OPORT6
OPORT7
VSS
VDD2
RAMA9
RAMA8
RAMA7
SDOB2
SDOB1
SDOB0
SDBCK1
SDWCK1
VSS
SI SO VSS RAMD7 RAMD6 RAMD5 RAMD4 RAMD3 RAMD2 RAMD1 RAMD0 VDD1 RAMA2 SCK /CS /CSB RAMA3 TEST /IC RAMA4 VSS RAMA5 RAMA6 /SDBCK0 SURENC KARA
OKE
MUTE CRC NONPCM VDD2
VSS
IPORT0
IPORT1
IPORT2
IPORT3
IPORT4
IPORT5
IPORT6
IPORT7
VDD2
VSS
RAMOEN
RAMWEN
RAMA1
RAMA0
SDIA1
SDIA0
SDBCK0
SDWCK0
VDD2
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50 51
52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80
82
83
84
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
81
CPO
DTSD
A
T
A
A
C3D
A
T
A
SDOB3
O
VFB
CPO XO XI
SDOB0
SDOB1
SDOB2
SDWCK1
SDBCK1
OPORT0
7
IPORT0
7
SO
SI
SCK
/CS
OVFB RAMA0
16
RAMOEN RAMWEN RAMCEN RAMD0
7
SDIB2 SDIB1 SDIB0 SDOA2 SDOA1 SDOA0
Delay RAM
SDIASEL
SDIA1
SDIA0
SDWCK0
SDBCK0
/SDBCK0
/CSB
SCK
Coefficient/
Program RAM
SI
SDOACKSEL SDIBCKSEL SDOBCKSEL
(30MHz)
CRC
ERAMUSE
SDOB Interface
24 * 16
Sub DSP
SDIB Interface
SDOA Interface
SDIBSEL
SDIA Interface
24 * 24
Main DSP
decoder
Control signals Control signals
Control Registers
Microprocessor
Interface
Input Buffer
AC-3/Pro Logic/DTS
Data RAM
External RAM
interface
STREAM0 7
PLL
Operating clock
L, R
LS, RS
C, LFE
SDOB3
SDIB3
SURENC
KARAOKE
MUTE
CRC
AC3DATA
DTSDATA
NONPCM
33 34
5. MICROPROCESSOR AND IC DATA
IC31:YSS912
1. Block Diagram
2. Pin Configuration
3. Pin Functions
No.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
O
Is+
Is
Ot
Is
Is
O
I
I
I
I
O
O
O
O
I+
I+
I+
I+
I+
I+
I+
I+
I+/O
I+/O
I+/O
I+/O
I+/O
I+/O
I+/O
I+/O
Is
I+
I+
A
I+
I+
I+
I+
I
Name FUNCTION I/O
1 VDD1 +5V power supply (for I/Os)
2 RAMCEN External SRAM interface /CE
3 RAMA16 External SRAM interface address 16
4 RAMA15 External SRAM interface address 15
5 SDIB0 PCM input 0 to Sub DSP
6 SDIB1 PCM input 1 to Sub DSP
7 SDIB2 PCM input 2 to Sub DSP
8 XI Crystal oscillator connection (12.288 MHz)
9 XO Crystal oscillator connection
10 VSS Ground
11 AVDD +3.3V power supply (for PLL circuit)
12 SDIB3 PCM input 3 to Sub DSP
13 TEST Test terminal (to be open in normal use)
14 TEST Test terminal (to be open in normal use)
15 OVFB Detection of overflow at Sub DSP
16 DTSDATA Detection of DTS data
17 AC3DATA Detection of AC-3 data
18 SDOB3 PCM output from Sub DSP
19 CPO Output terminal for PLL, to be connected to ground through the external analog filter circuit
20 AVSS Ground (or PLL circuit)
21 VDD2 +3.3V power supply (for core logic)
22 SDOA2 PCM output from Main DSP (C, LFE)
23 SDOA1 PCM output from Main DSP (LS, RS)
24 SDOA0 PCM output from Main DSP (L, R)
25 RAMA14 External SRAM interface address 14
26 RAMA13 External SRAM interface address 13
27 RAMA12 External SRAM interface address 12
28 RAMA11 External SRAM interface address 11
29 RAMA10 External SRAM interface address 10
30 VSS Ground
31 VDD1 +5V power supply (for I/Os)
32 OPORT0 Output port for general purpose
33 OPORT1 Output port for general purpose
34 OPORT2 Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Output port for general purpose
Ground 35 OPORT3
36 OPORT4
37 OPORT5
38 OPORT6
39 OPORT7
40 VSS
41 VDD2 +3.3V power supply (for core logic)
42 RAMA9 External SRAM interface address 9
43 RAMA8 External SRAM interface address 8
External SRAM interface address 7
44 RAMA7
45 SDOB2 PCM output from Sub DSP
PCM output from Sub DSP
PCM output from Sub DSP
46 SDOB1
47 SDOB0
48 SDBCK1 Bit clock input for SDOA, SDIB, SDOB
49 SDWCK1 Word clock input for SDOA, SDIB, SDOB
50 VSS Ground
51 VDD2 +3.3V power supply (for core logic)
52 NONPCM Detection of non-PCM data
53 CRC Detection of AC-3 CRC error
54 MUTE Detection of auto mute
55 KARAOKE Detection of AC-3 karaoke data
56 SURENC Detection of AC-3 2/0 mode Dolby surround encoded input
57 /SDBCK0 Inverted SDBCK0 colck output (refer to Block diagram)
58 RAMA6 External SRAM interface address 6
59 RAMA5 External SRAM interface address 5
60 VSS Ground
61 RAMA4 External SRAM interface address 4
62 /IC Initial clear
63 TEST Test terminal (to be open in normal use)
64 RAMA3 External SRAM interface address 3
65 /CSB Sub DSP Chip select
66 /CS Microprocessor interface Chip select input
67 SO Microprocessor interface Serial data output
68 SI Microprocessor interface / Sub DSP Serial data input
69 SCK Microprocessor interface / Sub DSP clock input
70 RAMA2 External SRAM interface address 2
71 VDD1 +5V power supply (for I/Os)
72 RAMD0 External SRAM interface data (STREAM0 output when External SRAM is not in use)
73 RAMD1 External SRAM interface data (STREAM1 output when External SRAM is not in use)
External SRAM interface data (STREAM2 output when External SRAM is not in use)
External SRAM interface data (STREAM3 output when External SRAM is not in use)
External SRAM interface data (STREAM4 output when External SRAM is not in use)
External SRAM interface data (STREAM5 output when External SRAM is not in use)
External SRAM interface data (STREAM6 output when External SRAM is not in use)
External SRAM interface data (STREAM7 output when External SRAM is not in use)
74 RAMD2
75 RAMD3
76 RAMD4
77 RAMD5
78 RAMD6
79 RAMD7
80 VSS Ground
81 VDD2 +3.3V power supply (for core logic)
82 SDWCK0 Word clock input for SDIA, SDOA, SDIB, SDOB
83 SDBCK0
Bit clock input for SDIA, SDOA, SDIB, SDOB
84 SDIA0 AC-3 bitstream (or PCM) data input for Main DSP
85 SDIA1 AC-3 bitstream (or PCM) data input for Main DSP
86 RAMA1 External SRAM interface address 1
External SRAM interface address 0 87 RAMA0
88 RAMWEN External SRAM interface /WE
External SRAM interface /OE 89 RAMOEN
90 VSS Ground
91 VDD2 +3.3V power supply (for core logic)
92 IPORT7 Input port for general purpose
93 IPORT6 Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
Input port for general purpose
94 IPORT5
95 IPORT4
96 IPORT3
97 IPORT2
98 IPORT1
99 IPORT0
100 VSS Ground
I+ : Input terminal with a pull-up resistor
O : Digital output terminal
Ot : Tri-state digital output terminal
A : Analog terminal
NOTE) Is : Schmidt trigger input terminal