Functional Block Diagram
Left/Right
Left Surround/
Right Surround
Xtal
Center/
Subwoofer
S/PDIF Input
Data
A
E
F
Address
Test
Control
General Purpose I/O Ports
Host
Parallel Port
Serial Output Ports
Serial Input Ports
G
B
C
D
4
16
20
Serial
Host
Interface
Internal
Program/ Data
ROM
16k x 32
Internal
Program RAM
1k x 32
Internal Data
RAM
9k x 20
4
Serial
Audio
Inputs
S/PDIF
Receiver
Parallel
Host
Interface
Input
FIFO
8 x 9
S/PDIF
Transmitter
Serial
Audio
Outputs
Memory
Interface
ICE
Interface
System
Oscillator
& DSP PLL
Audio
PLL
GPIO
ZR38001
DSP Core
6
Left/Right
(S/PDIF)
4
A0
GND
SS
TMS
INT
VDD
D14/RDY
GND
A1
A2
A3
VDD
D13/ C/D
MUTE/GPIO5
D12/ERR
A4
VDD
GPIO4
GND
A5
A6
D11/PP7
GPIO3
A7
A8
D10/PP6
A9
A10
GND
VDD
A1
1
D9
/PP5
D8
/PP4
SO
VDD
GND
A1
2
TD
O
A1
3
D7
/PP3
D6
/PP2
A1
4
GND
VDD
A1
5
D5
/PP1
D4
/PP0
A1
6
RD
GND
SDB
SDC
GND
A19
A18
A17
D18
D19
CLKOUT
GND
VDDA
FLTCAP
GNDA
VDD
SCKIN
GND
XTI
XTO
P/M
SPFRX
BYPASS
VDD
DREQ/GPIO0
ERROR/GPIO1
GPIO2
VDD
SDD
GND
CS
WR
D1
5
S
D
G/S
P
F
T
X
D1
6
SCK
B
D1
7
WSB
/F
S
B
SDF
VDD
WSA
/F
S
A
SCK
A
GND
SI
TD
I
SCK
TC
K
SDE
VDD
SDA
RES
ET
VDD
Pin 1 index mark,
notched corner, or both
ZR38600
(TOP VIEW)
1
30
51
80
100
31
50
81
20
A0-7, I0-7,
M0-7, SP
Address
Register
File
3 x 8 x 20
1 x 20
AALU
20
20
20
A
I
M
20
20
Data Bus
32
Program Data Bus
DBX
12
20
Mu
x
20
Data Address Bus
14
Program Address Bus
20
Mux
Loop Start
Stack
Program Counter
Increment
32
Mode Register
Z Register
Clock PLLs &
Oscillators
Reset
External Interrupt
Xtal
RESET
INT
2
D0-D1
D2-D7
Data
Register
File
2 x 48
6 x 20
Multiplier
20 x 20
S
h
ifter
Mux
DS
48
2
Data Shifter
20
MS
1
48
20
48
Status
ALU
Barrel
Shifter
48
Mu
x
2 x 48
SD
1
48
48
Input Control
Output Control
2
3
20
Mu
x
Instruction Unit
Program Sequence Unit
Address Generation Unit
Memory
System Interfaces
Arithmetic Unit
Input/Output Ports
Detailed Block Diagram
20
20
Demux
32
14
10
Mux
ICE I/F
4
Test
Serial Host I/F
4
Host
GPIOC[5:0]
15
32
Data
Control
4
Parallel
Port
Interrupt Mask
12
Mu
x
42
48
A
dder
48
20
Instruction
Register
Repeat
Count
Loop Count
Stack
Compare
Loop End
Stack
SDE
SRG
GPIO[5:0]
E Input
F Input
G Output/
Serial
Ports
A Input
B Output
C Output
D Output
GPIO[5:0]
SDA
SDB
SDC
General
Purpose
Ports
16
Data
20
Addr
Program/Data
ROM
16k x 32
Data RAM
9k x 20
Program/Data
RAM
1k x 32
S/PDIF
Receiver
S/PDIF Input
SDD
SRA
SRB
SRC
SRD
SRE
SRF
SDF
SDG
Memory
Control
Interface
Port
Control
Parallel
Data FIFO
8 x 9
9
2
S/PDIF
Transmitter
S/PDIF Output
CRC
Logic
18
Control
3
Clocks &
Control
Voltage Reference
Serial Output Interface
Digital
Filter
High
Pass
Filter
High
Pass
Filter
Decimation
Digital
Filter
Decimation
LP Filter
DAC
-
+
-
+
S/H
LP Filter
DAC
-
+
-
+
S/H
AINR+
VA
SCLK
SDATA MCLKD
PDN
14
16
20
19
24
27
VCOM
2
MCLKA
7
LRCK
13
ADCTL
6
LGND
22
TSTO1
8
AINR-
26
Comparator
Comparator
AINL+ 4
AINL- 5
VREF
1
DFS
18
S/M
17
AGND
3
AGND
25
AGND
28
23
VL
TSTO2
21
VD
11
DGND
12
Calibration
Microcontroller
CAL
10
DACTL
9
DGND
15
49
50
QK01:CS5394
Q651:ZR38600
Power Supply Connections
VA - Analog Power, Pin 24.
Positive analog supply. Nom5 volts.
VL - Logic Power, Pin 23.
Positive logic supply for the analog section. Nom5 volts.
AGND - Analog Ground, Pins 3, 25, and 28.
Analog ground reference.
LGND - Logic Ground, Pin 22.
Ground reference for the logic portions of the analog section.
VD - Digital Power, Pin 11.
Positive supply for the digital section. Nom5 volts.
DGND - Digital Ground, Pins 12 and 15.
Digital ground reference for the digital section.
Analog Inputs
AINR-, AINR+ - Differential Right Channel Analog Inputs, Pins 26 and 27.
Analog input connections for the right channel differential inputs. Nominally 4.0 Vpp
differential for full-scale digital output.
AINL-, AINL+ - Differential Left Channel Analog Inputs, Pins 4 and 5.
Analog input connections for the left channel differential inputs. Nominally 4.0 Vpp
differential for full-scale digital output.
Analog Outputs
VCOM - Common Mode Voltage Output, Pin 2.
Nom2.5 volts. Requires a 10 mF electrolytic capacitor in parallel with 0.1 mF
ceramic capacitor for decoupling to AGND. Caution is required if this output be used
to bias the analog input buffer circuits. Refer to the CDB5394 as an example.
VREF - Voltage Reference Output, Pin 1.
Nom4 volts. Requires a 100 mF electrolytic capacitor in parallel with 0.1 mF
ceramic capacitor for decoupling to AGND.
Digital Inputs
ADCTL - Analog Control Input, Pin 6.
Must be connected to DACTL. This signal enables communication between the analog
and digital circuits.
DFS - Digital Format Select, Pin 18.
The relationship between LRCK, SCLK and SDATA is controlled by the DFS pin.
When high, the serial output data format is I 2 S compatible. The serial data format
is left-justified when low.
CAL - Calibration, Pin 10.
Activates the calibration of the tri-level delta-sigma modulator on the rising edge of
the CAL input.
MCLKA - Analog Section Input Clock, Pin 7.
This clock is internally divided and controls the delta-sigma modulators. An MCLKA
frequency of 12.288 MHz sets a modulator sampling rate of 3.072 MHz and a output
sample rate of 48 kHz. MCLKA must be connected to MCLKD.
MCLKD - Digital Section Input Clock, Pin 20.
MCLKD clocks the digital filter and must be connected to MCLKA. The required
MCLKD frequency is determined by the desired sample rate. A MCLKD of 12.288MHz
corresponds to Fs equal to 48 kHz. MCLKA must be connected to MCLKD.
PDN - Power Down, Pin 19.
When high, the device enters power down. Upon returning low, the device enters
normal operation and issues commands to initialize the voltage reference and
synchronize the analog and digital sections of the device.
S/M - Slave or Master Mode, Pin 17.
When high, the device is configured for Slave mode where LRCK and SCLK are
inputs. The device is configured for Master mode where LRCK and SCLK are outputs
when S/M is low.
Digital Outputs
DACTL- Digital to Analog Control Output, Pin 9.
Must be connected to ADCTL. This signal enables communication between the
digital and analog circuits.
SDATA - Digital Audio Data Output, Pin 16.
The 24-bit audio data is presented MSB first, in 2’s complement format. This pin has
a internal pull-down resistor and must remain low during the power-up sequence to
avoid accessing a test mode.
Digital Inputs or Outputs
LRCK - Left/Right Clock, Pin 13.
LRCK determines which channel, left or right, is to be output on SDATA. The
relationship between LRCK, SCLK and SDATA is controlled by the Digital Format
Select (DFS) pin. Although the outputs for each channel are transmitted at different
times, Left/Right pairs represent simultaneously sampled analog inputs. In master
mode, LRCK is an output whose frequency is equal to Fs. In Slave Mode, LRCK is
an input whose frequency must be equal to Fs.
SCLK - Serial Data Clock, Pin 14.
Clocks the individual bits of the serial data from SDATA. The relationship between
LRCK, SCLK and SDATA is controlled by the Digital Format Select (DFS) pin. In
master mode, SCLK is an output clock at 64•L Fs. In slave mode, SCLK is an input
which requires a continuously supplied clock at any frequency from 48•L to 128•L
Fs (64•L is recommended).
Miscellaneous
TSTO1, TSTO2 - Test Outputs, Pins 8 and 21.
These pins are intended for factory test outputs. They must not be connected to any
external component or any length of circuit trace.
1
2
3
4
5
6
7
8
21
22
23
24
25
26
27
28
AGND
AINR+
AINR-
AGND
VA
VL
LGND
TSTO2
TSTO1
MCLKA
ADCTL
AINL-
AINL+
AGND
VCOM
VREF
9
10
11
12
17
18
19
20
MCLKD
PDN
DFS
S/M
DGND
VD
CAL
DACTL
13
14
15
16
SDATA
DGND
SCLK
LRCK
TEST OUTPUT
ANALOG SECTION CLOCK INPUT
ANALOG CONTROL DATA INPUT
LEFT CHANNEL ANALOG INPUT-
LEFT CHANNEL ANALOG INPUT+
ANALOG GROUND
COMMON MODE VOLTAGE OUTPUT
VOLTAGE REFERENCE
DIGITAL GROUND
DIGITAL SECTION POWER
CALIBRATION
CONTROL DATA OUTPUT
SERIAL CLOCK
LEFT/RIGHT CLOCK
ANALOG GROUND
RIGHT CHANNEL ANALOG INPUT+
RIGHT CHANNEL ANALOG INPUT-
ANALOG GROUND
POSITIVE ANALOG POWER
ANALOG SECTION LOGIC POWER
ANALOG SECTION LOGIC GROUND
TEST OUTPUT
DIGITAL SECTION CLOCK INPUT
POWER DOWN
SERIAL DATA FORMAT SELECT
SLAVE/MASTER MODE
SERIAL DATA OUTPUT
DIGITAL GROUND
