1-24
SCLK
MCLK
M4
LRCK
SDATA
AOUTL+
AOUTR+
SERIAL INTERFACE
AND FORMAT SELECT
INTERPOLATION
SOFT MUTE
DS
MODULATOR
DYNAMIC
DE-EMPHASIS
SWITCHED
AOUTL-
AOUTR-
FILT+
FILTER
INTERPOLATION
FILTER
FILTER
MULTI-BIT
DS
MODULATOR
MULTI-BIT
ELEMENT
MATCHING
LOGIC
DYNAMIC
ELEMENT
MATCHING
LOGIC
CAPACITOR-DAC
AND FILTER
SWITCHED
CAPACITOR-DAC
AND FILTER
VREF
CMOUT
FILT-
VOLTAGE REFERENCE
HARDWARE MODE CONTROL
CLOCK
DIVIDER
(CONTROL PORT)
(AD0/CS)
M3
M2
(AD1/CDIN) (SCL/CCLK)
M1
M0
(SDA/CDOUT)
RESET
MUTEC MUTE
S C L K
A u dio
D ata
P ro cessor
E xternal C lo ck
M C L K
A G ND
A O U T R+
C S 4397
S D AT A
V A
A O UT R-
+5.5 V
A na lo g
+
M ode
S elect
(C ontro l P o rt)
M 1 (G N D )
M 0 (S D A /C DO U T )
A O UT L -
A O UT L+
D G ND
V D
M U T E
An alog
C ond itio nin g
An alog
C ond itio nin g
7
22
2 4
23
19
20
1 8
9
1
15
13
11
12
4
14
5
M 2 (S CL/C C LK )
L R CK
+
R S T
10
M 3 (A D 1/C D IN )
M 4 (AD 0/CS )
2
3
2 5
2 6
2 7
V R E F
F ILT +
FILT -
+5.5/3.5V
An alog
2 8
6
2 1
M U T E C
8
17
+
+
CM O U T
V D
16
C /H
3.3 V
D igital
1.8 IC DATA
QD01/QD31 CS4397
Block Diagram
Pin Configuration
1
4
2
3
Input
Output
GND
Specific IC
Output voltage
adjustment terminal
Block Diagram
Q801
PQ05RD21
1 DC input(Vin)
2 DC output(Vo)
3 GND
4 Output voltage adjustment
terminal(Vadj)
1
2
3 4
PQ15RW11
Pin Configuration
Q821
PQ09RF1
&
Summary of Contents for SA-14
Page 5: ...1 3 1 4 1 3 BLOCK DIAGRAM...
Page 6: ...1 4 WIRING DIAGRAM 1 5 1 6...
Page 7: ...1 7 1 8 1 5 SCHEMATIC DIAGRAM...
Page 8: ...1 9 1 10...
Page 9: ...1 11 1 12...
Page 10: ...SACD CD REP 1 TRACK RND PROGRAM TOTAL PLAY 1 13 1 14...
Page 11: ...1 15 1 16...
Page 12: ...1 17 1 18...
Page 14: ...PH16 PY16 QY05 QY03 QY06 QY07 QY61 QY12 1 21 1 22 QY01 QY08...
Page 19: ...1 27 1 28...