Marantz SA-12S1, Service Manual

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5.5.3 Reset circuitry
Reset of Sti5505:
In power down mode STB_CONT is high; the clock is
disabled in order to reduce the power consumption. When
STB_CONT goes low, STB_CONTD goes high and enables
the 27 MHz clock.
Check that this clock is present and stable before the
RESETn is de-asserted. RESETn is a signal, which allows
initialising the main processor. We check also that when
going from ON mode to stand-by mode, the 27 MHz is held
for a certain moment after RESETn is asserted.
Reset of Servo:
The reset for the Servo circuit is given on Power On to the
MACE IC 7207 with POR via C2215, R3234 and D6200. The
reset signals STB_DALAS for DALAS and PORN for
HD61are generated by MACE IC.
When POR is not working (due to a hang-up situation), an
extra reset signal RSTN, coming from the Sti5505 will wake
up the Servo circuit.
5.5.4 Clock check
The source clock comes from the DAC board. The SACD
CLK is a master clock from which all the other clocks are
derived. If this one is not present the system cannot start and
work.
The SACD power supply, the mono board and the DAC
board should be connected together. On power up the clocks
appear on the board. All clocks to be measured have a 0.02%
tolerance.
Clockname Test point Frequency / level
384Fs_in F911 16.9344 MHz / 3V3
SACD_CLK F903 16.9344 MHz / 5V
27M_CLK F503 27MHz / 5V
PCMCLK_AV F640 12.288MHz / 3V3
MACE CLOCK F211 8.46 MHz / 3V3
PM3394B
ch1
ch1: freq= 16.9MHz
CH1 1.00 V~ MTB20.0ns ch1+
1
384FS_IN
CL 06532152_016.eps
051200
PM3394B
ch1
ch1: freq= 16.9MHz
CH1 1.00 V~ MTB20.0ns ch1+
1
SACD CLK
CL 06532152_017.eps
051200
PM3394B
ch1
ch1: freq= 27.0MHz
CH1 1.00 V~ MTB20.0ns ch1+
1
27M_CLK
CL 06532152_018.eps
051200
PM3394B
ch1
ch1: freq= 12.2MHz
CH1 1.00 V~ MTB50.0ns ch1+
1
PCM CLK_AV
CL 06532152_019.eps
051200