65
Pin Descriptions
Output Pins
Pin Name
Pin #
Type
Description
QE23-
QE0
See
SiI
1161
Pin
Diagram
Out
Output Even Data[23:0] corresponds to 24-bit pixel data for one pixel per clock input mode
and to the first 24-bit pixel data for two pixels per clock mode.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
QO23-
QO0
See
SiI
1161
Pin
Diagram
Out
Output Odd Data[23:0] corresponds to the second 24-bit pixel data for two pixels per clock
mode. During one pixel per clock mode, these outputs are driven low.
Output data is synchronized with output data clock (ODCK).
Refer to the TFT Panel Data Mapping section, which tabulates the relationship between the
input data to the transmitter and output data from the receiver.
A low level on PD# or PDO# will put the output drivers into a high impedance (tri-state) mode.
A weak internal pull-down device brings each output to ground.
ODCK
44
Out
Output Data Clock. This output can be inverted using the OCK_INV pin. A low level on PD# or
PDO# will put the output driver into a high impedance (tri-state) mode. A weak internal pull-
down device brings the output to ground.
DE
46
Out
Output Data Enable. This signal qualifies the active data area. A HIGH level signifies active
display time and a LOW level signifies blanking time. This output signal is synchronized with
the output data. A low level on PD# or PDO# will put the output driver into a high impedance
(tri-state) mode. A weak internal pull-down device brings the output to ground.
HSYNC
VSYNC
CTL1
CTL2
CTL3
48
47
40
41
42
Out
Horizontal Sync output control signal.
Vertical Sync output control signal.
General output control signal 1. This output is
not
powered down by PDO#.
General output control signal 2.
General output control signal 3.
A low level on PD# or PDO# will put the output drivers (except CTL1 by PDO#) into a high
impedance (tri-state) mode. A weak internal pull-down device brings each output to ground.
Differential Signal Data Pins
Pin Name
Pin #
Type
Description
RX0+
RX0-
RX1+
RX1-
RX2+
RX2-
90
91
85
86
80
81
Analog Receiver Differential Data Pins. TMDS Low Voltage Differential Signal input data pairs.
RXC+
RXC-
93
94
Analog Receiver Differential Clock Pins. TMDS Low Voltage Differential Signal input clock pair.
EXT_RES 96 Analog
Impedance Matching Control. An external 390
:
resistor must be connected between AVCC
and this pin.
IC11 IC12 (DVI PCB) : SiI 1161
Summary of Contents for PS7500
Page 25: ...27 28 TO AUX1 PCB TO FRONT PCB TO INPUT PCB TO USB PCB TO INPUT PCB DSP PCB 2 2 ...
Page 27: ...31 32 CN82 AMP PCB ...
Page 33: ...43 44 to STANDBY PCB POWER PCB ...
Page 37: ...51 52 DSP PCB B IC20 Q112 IC16 Q125 DVI PCB IC17 IC11 IC12 IC16 IC18 Q104 Q103 Q102 Q101 ...
Page 39: ...55 56 FRONT PCB IC81 Q801 H P PCB TUNER PCB AUX1 PCB IC83 IC84 SBLR PCB Q103 ...
Page 48: ...68 IC38 IC39 DSP PCB TC74VHC157 ...
Page 50: ...70 IC23 INPUT PCB TC9162AN IC21 INPUT PCB TC9164AN ...
Page 51: ...71 IC23 INPUT PCB TC9162AN IC21 INPUT PCB TC9164AN ...
Page 52: ...72 IC11 IC12 VOLUME PCB TC9482 ...
Page 53: ...73 IC11 IC12 VOLUME PCB TC9482 ...
Page 61: ...81 IC23 DSP PCB CS4382 ...
Page 62: ...82 IC23 DSP PCB CS4382 ...
