Marantz ER3000, Service Manual

Page: 19 / 78

31 32
SDOS
LOOP1
1
I2C
4
4
2
SMUTE 3
BICK 4
LRCK 5
SDTI1 6
SDTI2 7
SDTI3 8
SDTO 9
DAUX 10
DFS 11
LOOP0/SDA/CDTI
4
3
DIF1/SCL/CCLK
42 41 4
0
MCLK
39
DZF1
38
AVSS
3
7
AVDD
36
VREFH
35
VCOM
34
NC
12
DZFE
13
TVDD
14
DVDD
15
DVSS
16 17
TST
18
NC
19
ADIF
20
CAD1
21
CAD0
22
33
32
31
30
29
28
27
26
25
24
23
DZF2/OVF
RIN+
RIN-
LIN+
LIN-
ROUT1
LOUT1
ROUT2
LOUT2
ROUT3
LOUT3
AK4527BVQ
Top View
PDN
DIF0/CSN P/S
Audio
I/F
LPF
LPF DAC
DATT
LPF DAC DATT
LPF DAC DATT
LPF DAC
DATT
LPF DAC DATT
LOUT1
ROUT1
LOUT2
ROUT2
LOUT3
ROUT3
DAC DATT
AK4527B
ADC HPF
ADC
HPF
RIN-
RIN+
LIN-
LIN+
LRCK
BICK
SDOUT1
SDOUT2
SDOUT3
AC3
SDIN
MCKO
LRCK
BICK
XTI
XTO
DIR
SDTO
AK4112A
RX4 RX3 RX2 RX1
LRCK
BICK
SDTI1
SDTI2
SDTI3
DAUX
SDOS
MCLK
LRCK
BICK
SDOUT
SDIN1
SDIN2
SDIN3
MCLK
SDTO
Format
Converter
No. Pin Name I/O Function
1 SDOS I SDTO Source Select Pin (Note 1)
"L": Internal ADC output, "H": DAUX input
2 I2C I Control Mode Select Pin
"L": 3-wire Serial, "H": I
2 C Bus
3 SMUTE I Soft Mute Pin (Note 1)
When this pin goes to "H", soft mute cycle is initialized.
When returning to "L", the output mute releases.
4 BICK I Audio Serial Data Clock Pin
5 LRCK I Input Channel Clock Pin
6 SDTI1 I DAC1 Audio Serial Data Input Pin
7 SDTI2 I DAC2 Audio Serial Data Input Pin
8 SDTI3 I DAC3 Audio Serial Data Input Pin
9 SDTO O Audio Serial Data Output Pin
10 DAUX I AUX Audio Serial Data Input Pin
11 DFS I Double Speed Sampling Mode Pin (Note 1)
"L": Normal Speed, "H": Double Speed
12 NC - No Connect
No internal bonding.
13 DZFE I Zero Input Detect Enable Pin
"L": mode 7 (disable) at parallel mode,
zero detect mode is selectable by DZFM2-0 bits at serial mode
"H": mode 0 (DZF1 is AND of all six channels)
14 TVDD -
Output Buffer Power Supply Pin, 2.7V~5.5V
15 DVDD -
Digital Power Supply Pin, 4.5V~5.5V
16 DVSS - Digital Ground Pin, 0V
17 PDN I Power-Down & Reset Pin
When "L", the AK4527B is powered-down and the control registers are reset to default
state. If the state of P/S or CAD0-1 changes, then the AK4527B must be reset by PDN.
18 TST I Test Pin
This pin should be connected to DVSS.
19 NC - No Connect
No internal bonding.
20 ADIF I Analog Input Format Select Pin
"H": Full-differential input, "L": Single-ended input
21 CAD1 I Chip Address 1 Pin
22 CAD0 I Chip Address 0 Pin
QK01 : AK4527
BLOCK DIAGRAM
PIN CONFIGURATION
PIN FUNCTION
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