Marantz DV2400, Service Manual

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LCS1#
LOE#
LD0
VSS
LCS3#
LCS2#
I2CDATA/AUX[0]
LA
21
LA
20
RE
S
E
T
#
VE
E
NC
H
IO
C
S
16#/
C
A
M
C
LK
/A
U
X
3[
4
]
HA
1
/A
U
X
4
[3
]
VS
S
HA
0
/A
U
X
4
[2
]
HW
R#
/DCI
_
C
L
K
/A
UX
4
[5
]
HRD#
/DCI
_
A
C
K
#
/A
U
X
4
[6
]
HD4
/DCI
4
/A
U
X
1
[4
]
HD5
/DCI
5
/A
U
X
1
[5
]
HD6
/DCI
6
/A
U
X
1
[6
]/
V
F
D_
DO
UT
HD2
/DCI
2
/A
U
X
1
[2
]
HD3
/DCI
3
/A
U
X
1
[3
]
VE
E
VCC
DB8
VC
C
DB5
DB9
DCS0#
VC
C
VS
S
T
S
D
0
/SEL
_
P
L
L
0
T
S
D
1
/SEL
_
P
L
L
1
TD
M
F
S
TD
M
C
L
K
TD
M
D
R
TD
M
T
S
C
#
T
W
S/
SEL
_
P
L
L
2
VE
E
LA
4
LA
5
LA
6
LA
7
LA
8
LA
9
VS
S
VC
C
LA
10
LA
11
LA
12
LA
13
LA
14
LA
15
LA
16
VS
S
VE
E
LA
17
LA
18
LA
19
T
D
M
D
X
/R
SEL
VS
S
TS
D
2
SP
D
IF
/PL
L
3
NC
VS
S
MC
L
K
TB
C
K
VEE
VEE
VS
S
VSS
DQM
RS
D
RWS
RB
CK NC
XI
N
XO
U
T
AV
E
E
DSCK
VSS
DB15
DB13
DB11
DB1
VSS
DMBS1
DRAS#
DOE#/DSCK_EN
VEE
DMA9
DMA7
VSS
DMA5
DMA3
VEE
DCS1#
DB14
DB12
DB10
DB0
VEE
DMBS0
DWE#
DCAS#
VSS
DMA8
DMA6
VEE
DMA4
DMA2
VSS
DB7
DB6
VSS
DB4
DB3
DB2
DMA11
DMA10
DMA1
DMA0
HCS
3
F
X
#
/A
UX
3
[6
]
HCS
1
F
X
#
/A
UX
3
[7
]
VS
S
HI
O
RDY
/A
UX
3
[3
]
VS
S
H
D
1
3
/A
U
X
2
[5
]/S
P
H
D
1
2
/A
U
X
2
[4
]/C
2P
O
H
D
11/A
U
X
2[3
]//IR
Q
H
D
1
0
/A
U
X
2
[2
]/S
Q
S
K
HD9
/A
UX
2
[1
]/
S
Q
S
O
HD8
/DCI
_
F
DS
#
/A
U
X
2
[0
]/
V
F
D
_
C
L
k
VS
S
HI
RQ
/D
CI
_
E
RR#
/A
UX
4
[7
]
H
R
S
T
#
/A
U
X
3[
5]
HRRQ
#
/A
U
X
4
[0
]
HW
RQ#/
DCI
_RE
Q
#/
A
U
X
4
[1
]
H
D
1
5
/A
U
X
2
[7
]/I
R
H
D
1
4
/A
U
X
2
[6
]/S
Q
S
I
VC
C
HD7
/DCI
7
/A
U
X
1
[7
]/
V
F
D_
DI
N
HD1
/DCI
1
/A
U
X
1
[1
]
HD0
/DCI
0
/A
U
X
1
[0
]
VC
C
VS
S
H
S
Y
N
C
#
/C
AM
IN
7
/AU
X3
[0
]
P
C
L
K
2
X
S
CN/
CA
M
IN4
YU
V
7
/C
AM
IN
3
YU
V
6
/V
D
A
C
P
C
L
K
Q
S
CN/
CA
M
IN5
/A
UX
3
[2
]
VS
YN
C
#
/C
AM
IN
6
/AU
X
3
[1
]
YU
V
5
/Y
D
A
C
VS
S
AD
V
E
E
YU
V
4
/R
SE
T
YU
V
3
/C
O
M
P
Y
U
V
2
/CDA
C
YU
V
1
/V
R
E
F
YU
V
0
/C
AM
IN
2
/U
D
A
C
DCL
K
VE
E
AUX[7]/STALL#
AUX[6]
VEE
LD1
LD2
LA3
LD12
VEE
HA2/AUX4[4]
VEE
VEE
LD3
LD5
LD9
LD13
LWRHL#
CAMIN1
I2C_CLK/AUX[1]
AUX[3]/IOR#
LD4
LD6
LD10
LD14
VSS
LA0
AUX[2]/IOW#
AUX[4]
VEE
LD7
LD11
LD15
VEE
LA1
VSS
AUX[5]
VSS
LD8
VSS
LWRLL#
CAMIN0
LA2
VSS
VCC
LCS0#
VSS
208-Pin PQFP Package
ES6028F
IC1:ES6028
ES6028 PIN DESCRIPTION
Table 1 lists the pin descriptions for the ES6028.
Table 1 ES6028 Pin Description
Name Pin Numbers I/O Definition
VEE
1,18, 27, 59, 68, 75,
92, 99, 104, 130,
148, 157, 159, 164,
183, 193, 201
I I/O power supply.
LA[21:0]
2:7, 10:16, 19:23,
204:207
O RISC port address bus.
VSS
8, 17, 26, 34, 43,
52, 60, 67, 76, 84,
91, 98, 103, 112,
120, 129, 138, 147,
156, 163, 171, 177,
184, 192, 200, 208
I Ground.
VCC
9, 35, 44, 83, 121,
139, 172
I Core power supply.
RESET# 24 I Reset input, active-low.
TDMDX
25
O TDM transmit data output.
RSEL
I LCS3 ROM Boot Data Width Select. Strapped to VCC or ground via 4.7-k
Ω
resistor; read only during reset.
TDMDR 28 I TDM receive data input.
TDMCLK 29 I TDM clock input.
TDMFS 30 I TDM frame sync input.
TDMTSC# 31 O TDM output enable.
TWS
32
O Audio transmit frame sync output.
SEL_PLL2
I System and DSCK output clock frequency selection is made at the rising edge of
RESET#. The matrix below lists the available clock frequencies and their
respective PLL bit settings. Strapped to VCC or ground via 4.7-k
Ω resistor; read
only during reset.
RSEL Selection
0 16-bit ROM
1 8-bit ROM
SEL_PLL2 SEL_PLL1 SEL_PLL0 Clock Type
0 0 0 DCLK x 4.25
0 0 1 Reserved
0 1 0 Bypass mode
0 1 1 DCLK x 3.75
1 0 0 DCLK x 4.5
1 0 1 Reserved
1 1 0 DCLK x 3.5
1 1 1 DCLK x 4
TSD0
33
O Audio transmit serial data port 0.
SEL_PLL0 I Refer to the description and matrix for SEL_PLL2 pin 32.
TSD1
36
O Audio transmit serial data port 1.
SEL_PLL1 I Refer to the description and matrix for SEL_PLL2 pin 32.
TSD2 37 O Audio transmit serial data port 2.
NC 38, 42, 48 — No connect pins. Leave open.
MCLK 39 I/O Audio master clock for audio DAC.
TBCK 40 O Audio transmit bit clock.
SPDIF
41
O S/PDIF output.
SEL_PLL3
I Clock source select.Strapped to VCC or ground via 4.7-k
Ω
resistor; read only
during reset.
RSD 45 I Audio receive serial data.
RWS 46 I Audio receive frame sync.
RBCK 47 I Audio receive bit clock.
XIN 49 I 27-MHz crystal input.
XOUT 50 O 27-MHz crystal output.
AVEE 51 I Analog power for PLL.
DMA[11:0] 53:58, 61:66 O DRAM address bus.
DCAS# 69 O DRAM column address strobe.
DOE#
70
O DRAM output enable.
DSCK_EN O DRAM clock enable.
DWE# 71 O DRAM write enable.
DRAS# 72 O DRAM row address strobe.
DMBS0 73 O SDRAM bank select 0.
DMBS1 74 O SDRAM bank select 1.
DB[15:0] 77:82, 85:90, 93:96 I/O DRAM data bus.
DCS[1:0]# 97,100 O SDRAM chip select.
DQM 101 O Data input/output mask.
DSCK 102 O Output clock to SDRAM.
DCLK 105 I Clock input to PLL.
Table 1 ES6028 Pin Description (Continued)
Name Pin Numbers I/O Definition
SEL_PLL3 Clock Source
0 Crystal oscillator
1 DCLK input
YUV0
106
O YUV0 pixel output data.
CAMIN2 I Camera input 2.
UDAC
O Video DAC output.
Y: Luma component for YUV and Y/C processing.
C: Chrominance signal for Y/C processing.
U: Chrominance component signal for YUV mode.
V: Chrominance component signal for YUV mode.
YUV1
107
O YUV1 pixel output data.
VREF I Internal voltage reference to video DAC. Bypass to ground with 0.1-
µ
F capacitor.
YUV2
108
O YUV2 pixel output data.
CDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV3
109
O YUV3 pixel output data.
COMP I Compensation input. Bypass to ADVEE with 0.1-
µ
F capacitor.
YUV4
110
O YUV4 pixel output data.
RSET I DAC current adjustment resistor input.
ADVEE 111 I Analog power for video DAC.
YUV5
113
O YUV5 pixel output data.
YDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
Table 1 ES6028 Pin Description (Continued)
Name Pin Numbers I/O Definition
Pin 114 113 108 106
Value DAC V DAC Y DAC C DAC U
0 CVBS1 Y C N/A
1 CVBS1 Y C CVBS2
2 N/A Y C N/A
3 CVBS1 N/A N/A CVBS2
4 CVBS1 N/A N/A N/A
5 CVBS1 Y Pb Pr
6 N/A Y Pb Pr
7 SYNC G B R
8 CHROMA Y Pb Pr
9 CVBS1 G B R
10 CVBS1 G R B
11 SYNC G R B
12 N/A Y Pr Pb
13 CVBS1 Y Pr Pb
YUV6
114
O YUV6 pixel output data.
VDAC O Video DAC output. Refer to description and matrix for UDAC pin 106.
YUV7
115
O YUV7 pixel output data.
CAMIN3 I Camera YUV 3.
PCLK2XSCN
116
I/O 27-MHz video output pixel clock.
CAMIN4 I Camera YUV 4.
PCLKQSCN
117
O 13.5-MHz video output pixel clock.
CAMIN5 I Camera YUV 5.
AUX3[2] I/O Aux3 data I/O.
VSYNC#
118
I/O Vertical sync, active-low.
CAMIN6 I Camera YUV 6.
AUX3[1] I/O Aux3 data I/O.
HSYNC#
119
I/O Horizontal sync, active-low.
CAMIN7 I Camera YUV 7.
AUX3[0] I/O Aux3 data I/O.
HD[5:0]
122:127
I/O Host data bus lines 5:0.
DCI[5:0] I/O DVD channel data I/O.
AUX1[5:0] I/O Aux1 data I/O.
HD[6]
128
I/O Host data bus line 6.
DCI[6] I/O DVD channel data I/O.
AUX1[6] I/O Aux1 data I/O.
VFD_DOUT I VFD data output.
HD[7]
131
I/O Host data bus line 7.
DCI[7] I/O DVD channel data I/O.
AUX1[7] I/O Aux1 data I/O.
VFD_DIN I VFD data input.
HD[8]
132
I/O Host data bus line 8.
DCI_FDS# I/O DVD input sector start.
AUX2[0] I/O Aux2 data I/O.
VFD_CLK I VFD clock input.
HD[9]
133
I/O Host data bus line 9.
AUX2[1] I/O Aux2 data I/O.
SQSQ I Subcode-Q data.
Table 1 ES6028 Pin Description (Continued)
Name Pin Numbers I/O Definition
HD[10]
134
I/O Host data bus line 10.
AUX2[2] I/O Aux2 data I/O.
SQSK I Subcode-Q clock.
HD[11]
135
I/O Host data bus line 11.
AUX2[3] I/O Aux2 data I/O.
IRQ O IRQ.
HD[12]
136
I/O Host data bus line 12.
AUX2[4] I/O Aux2 data I/O.
C2PO I C2PO error correction flag from CD-ROM.
HD[13]
137
I/O Host data bus line 13.
AUX2[5] I/O Aux2 data I/O.
SP I 16550 UART serial port input.
HD[14]
140
I/O Host data bus line 14.
AUX2[6] I/O Aux2 data I/O.
SQSI I Subcode-Q sync.
HD[15]
141
I/O Host data bus line 15.
AUX2[7] I/O Aux2 data I/O.
IR I IR remote control input.
HWRQ#
142
O Host write request.
DCI_REQ# O DVD control interface request.
AUX4[1] I/O Aux4 data I/O.
HRRQ#
143
O Host read request.
AUX4[0] I/O Aux4 data I/O.
HIRQ
144
I/O Host interrupt.
DCI_ERR# I/O DVD channel data error.
AUX4[7] I/O Aux4 data I/O.
HRST#
145
O Host reset.
AUX3[5] I/O Aux3 data I/O.
HIORDY
146
I Host I/O ready.
AUX3[3] I/O Aux3 data I/O.
HWR#
149
I/O Host write.
DCI_CLK I/O DVD channel data clock.
AUX4[5] I/O Aux4 data I/O.
Table 1 ES6028 Pin Description (Continued)
Name Pin Numbers I/O Definition
HRD#
150
O Host read.
DCI_ACK# O DVD channel data valid.
AUX4[6] I/O Aux4 data I/O.
HIOCS16#
151
I Device 16-bit data transfer.
CAMCLK I Camera port pixel clock input.
AUX3[4] I/O Aux3 data I/O.
HCS1FX#
152
O Host select 1.
AUX3[7] I/O Aux3 data I/O.
HCS3FX#
153
O Host select 3.
AUX3[6] I/O Aux3 data I/O.
HA[2:0]
154, 155, 158
I/O Host address bus.
AUX4[4:2] I/O Aux4 data I/Os.
AUX[0]
160
I/O Auxiliary port 0 (open collector).
I2CDATA I/O I 2 C data I/O.
AUX[1]
161
I/O Auxiliary port 1 (open collector).
I2C_CLK I/O I 2 C clock I/O.
AUX[2]
162
I/O Auxiliary port.
IOW# O I/O Write strobe (LCS1).
AUX[3]
165
I/O Auxiliary port.
IOR# O I/O Read strobe (LCS1).
AUX[6:4] 166:168 I/O Auxiliary ports.
AUX[7]
169
I/O Auxiliary port.
STALL# I STALL# flag input; when set, extends cycle by adding wait states as required.
LOE# 170 O RISC port output enable.
LCS[3:0]# 173:176 O RISC port chip select.
LD[15:0]
178:182,
185:191,194:197
I/O RISC port data bus.
LWRLL# 198 O RISC port low-byte write enable.
LWRHL# 199 O RISC port high-byte write enable.
CAMIN0 202 I Camera YUV 0.
CAMIN1 203 I Camera YUV 1.
Table 1 ES6028 Pin Description (Continued)
Name Pin Numbers I/O Definition