18
PIN No.
NAME
I/ O
FUNCTIONAL DESCRIPTION
REMARKS
TEST0
HSO
UHSO
EMPH
LRCK
V
SS
BCK
AOUT
DOUT
MBOV
IPF
SBOK
CLCK
V
DD
V
SS
DATA
SFSY
SBSY
SPCK
SPDA
COFS
MONIT
V
DD
TESIO0
P2V
REF
HSSW
ZDET
PDO
TMAXS
TMAX
With pull-up resistor.
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
2-state output (PV
REF
,HiZ)
-
3-state output
(P2V
REF
,PV
REF,
V
SS
)
-
3-state output
(P2V
REF
,HiZ
,
V
SS
)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
Test mode terminal. Normally, keep at open.
Playback speed mode flag output terminal.
Subcode Q data emphasis flag output terminal.
Emphasis ON at “H” level and OFF at “L” level.
The output polarity can invert by command.
Channel clock output terminal. (44.1 kHz)
L-ch at “L” level and R-ch at “H” level.
The output polarity can invert by command.
Digital GND terminal.
Bit clock output terminal. (1.4112 MHz)
Audio data output terminal.
Digital data output terminal.
Buffer memory over signal output terminal.
Over at “H” level.
Correction flag output terminal.
At “H “ level, AOUT output is made to correction
impossibility by C
2
correction processing.
Subcode Q data CRCC check adjusting result output
terminal. The adjusting result is OK at “H” level.
Subcode P~W data readout clock input/output
terminal. This terminal can select by command bit.
Digital power supply voltage terminal.
Digital GND terminal.
Subcode P~W data output terminal.
Playback frame sync signal output terminal.
Subcode block sync signal output terminal.
Processor status signal readout clock output terminal.
Processor status signal output terminal.
Correction frame clock output terminal. (7.35 kHz)
Internal signal (DSP internal flag and PLL clock) output
terminal. Selected by command.
Digital power supply voltage terminal.
Test input/output terminal. Normally, keep at “L” level.
PLL double reference voltage supply terminal.
2/4 times speed at “VREF” voltage.
1 bit DA converter zero detect flag output terminal.
Phase difference signal output terminal of EFM signal
and PLCK signal.
TMAX detection result output terminal. Selected by
command bit (TMPS).
TMAX detection result output terminal. Selected by
command bit (TMPS).
-
O
O
O
O
-
O
O
O
O
O
O
I/O
-
-
O
O
O
O
O
O
O
-
I
-
O
O
O
O
O
UHSO
HSO
PLAYBACK SPEED
H
H
Normal
H
L
2 times
L
L
H
4 times
L
-
DIFFERENCE RESULT
TMAX OUTPUT
Longer than fixed ferq.
“P2V
REF
”
Shorter than fixed freq.
“V
SS
”
Within the fixed freq.
“HiZ”
PIN No.
NAME
I/ O
FUNCTIONAL DESCRIPTION
REMARKS
LPFN
LPFO
PV
REF
VCOREF
VCOF
AV
SS
SLCO
RFI
AV
DD
RFCT
RFZI
RFRP
FEI
SBAD
TSIN
TEI
TEZI
FOO
TRO
V
REF
RFGC
TEBC
TEBC
TEBC
DMO
2V
REF
SEL
FLGA
FLGB
FLGC
FLGD
V
DD
V
SS
IO0
IO1
IO2
IO3
Analog input.
Analog output.
-
-
Analog output.
-
Analog output.
Analog input (Zin : selected by command)
-
Analog input (Zin : 50k
)
Analog input.
Analog input.
Analog input.
Analog input.
Analog input.
Analog input.
Analog input (Zin : 10k
)
Analog output (2V
REF
~AV
SS
)
-
3-state PWM signal output.
(2V
REF
, V
REF
, V
SS
)
(PWM carrier = 88.2 kHz)
3-state PWM signal
output.(2VREF, VREF, VSS)
-
-
-
-
-
-
-
-
-
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
58
59
60
61
62
63
64
65
66
67
LPF amplifier inverting input terminal for PLL.
LPF amplifier output terminal for PLL.
PLL reference voltage supply terminal.
VCO center frequency reference level terminal.
Normally, keep at “PV
REF
” level.
VCO filter terminal.
Analog GND terminal.
Data slice level output terminal.
RF signal input terminal.
Analog power supply voltage terminal.
RFRP signal center level input terminal.
RFRP zero cross input terminal.
RF ripple signal input terminal.
Focus error signal input terminal.
Sub-beam adder signal input terminal.
Test input terminal. Normally, keep at “V
REF
” level.
Tracking error signal input terminal.
Track in at tracking servo on.
Trcaking error zero cross input terminal.
Focus servo equalizer output terminal.
Tracking servo equalizer output terminal.
Analog reference voltage supply terminal.
RF amplitude adjustment control signal output terminal.
Tracking balance control signal output terminal.
Feed equalizer output terminal.
Speed error signal or feed search equalizer output
terminal.
Disk equalizer output terminal. (PWM carrier = 88.2 kHz
for DSP, Synchronize to PXO)
Analog double reference voltage supply terminal.
APC circuit ON/OFF indication signal output terminal.
At the laser on time, UHF = L at “HiZ” level and
UHF = H at “H” level.
Extemal flag output terminal for internal signal.
Can select signal from TEZC, FOON, FOK and RFZC by
command.
Extemal flag output terminal for internal signal.
Can select signal from DECT, FOON, FMON and RFZC
by command.
Extemal flag output terminal for internal signal.
Can select signal from TRON, TRSR, FOK and SRCH by
command.
Extemal flag output terminal for internal signal.
Can select signal from TRON, DMON, HYS and SHC by
command.
Digital power supply voltage terminal.
Digital GND terminal.
General I/O terminal. Can change over input port or
output port by command. At the input mode time can
readout a state of terminal (H/L) by read command. At
the output mode time can control a state of terminal
(H/L/HiZ) by command.
I
O
-
I
O
-
O
I
-
I
I
I
I
I
I
I
I
O
O
-
O
O
O
O
O
-
O
O
O
O
O
-
-
I/O
1
100
99
Micom
Interface
LPF
1bit
DAC
Clock
generator
Correction
circuit
16K
RAM
Address
circuit
Digital out
Sub code
decoder
PLL TMAX
Data slicer
A
/ D
VCO
CLV servo
RAM
ROM
Digital equalizer
Servo
control
PWM
D / A
Automatic adjustment
circuit
Status
Synchronous
guarantee
EFM decode
Audio out
circuit
TEST
0
HSO
UHSO
EMPH
LRCK
VSS
BCK
AOUT
DOUT
MBOV
IPF
SBOK
CLCK
VDD
VSS
D
ATA
SFSY
SBSY
SPCK
SPDA
COFS
MONIT
VDD
TESIO 0
P2VREF
HSSW
ZDET
PDO
TMAXS
TMAX
XVDD
XO
XI
XVSS
VDD
PXO
PXI
VSS
TES I/N
TES IO1
DACT
CKSE
DMOUT
IO3
IO2
IO1
IO0
VSS
VDD
FLGD
FLGC
FLGB
FLGA
SEL
2VREF
DM/O
FVO
FMO
TEBC
RFGC
LPFN
LPFO
PVREF
VCOREF
VCOF
AVSS
SLCO
RF1
AVDD
RFCT
RFZI
RFRP
EF1
SBAD
TSIN
TEI
TEZI
FOO
TRO
VREF
RST
TSMOD
TEST4
CCE
BUCK
VSS
VDD
BUS3
BUS2
BUS1
BUS0
TEST3
TEST2
TEST1
DVSL
LO
DVR
DVDD
RO
DVSR
98
97
96
95
94
93
92
91
90
89
88
87
86
85
84
83
82
81
2
3
4
80
79
78
77
76
75
74
73
72
71
70
69
68
67
66
65
64
63
62
61
60
59
58
57
56
55
54
53
52
51
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
23
24
22
26
27
25
29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
44
45
46
47
48
49
50
28
IC62 : TC9462F (DIGITAL SIGNAL PROCESSOR)
BLOCK DIAGRAM
PIN FUNCTION
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