Patch Ideas: Analog Signal Processing, Voltage MATHS!
Envelope Follower
Apply signal to be followed to Signal Input CH. 1 or 4. Set Rise to 12:00. Set and or modulate Fall Time to achieve different
responses. Take output from associated Channel Signal Output for positive and negative Peak Detection. Take output from OR
buss Output to achieve more typical Positive Envelope Follower function.
Voltage Comparator/Gate Extraction w/ variable width
Apply signal to be compared to CH. 3 Signal Input. Set Attenuverter to greater than 50%. Use CH. 2 for comparing voltage (with
or without something patched). Patch SUM Output to CH. 1 Signal Input. Set CH. 1 Rise and Fall to full CCW. Take extracted Gate
from EOR. CH. 3 Attenuverter acts as the input level setting, applicable values being between 12:00 and Full CW. CH. 2 acts as
the threshold setting applicable values being from Full CCW to 12:00. Values closer to 12:00 are LOWER thresholds. Setting the
Rise more CW, you are able to Delay the derived Gate. Setting Fall more CW varies the width of the derived Gate. Use CH. 4 for
Envelope Follower patch, and CH. 3, 2 & 1 for Gate extraction, and you have a very powerful system for external signal
processing.
Full Wave Rectification
Mult signal to be rectified to both CH. 2 and 3 Input. CH 2 Scaling/ Inversion set to Full CW,CH. 3 Scaling/ Inversion set to Full
CCW. Take output from OR Output. Vary the Scaling.
Multiplication
Apply positive going control signal to be multiplied to CH.1 or 4 Signal Input. Set Rise to full CW, Fall to Full CCW. Apply positive
going, multiplier Control Signal to the BOTH Control Input. Take output from corresponding Signal Output.
Pseudo-VCA with clipping - Thanx to Walker Farrell
Patch audio signal to CH. 1, with Rise and Fall at full counter clockwise, or cycle CH. 1 at audio rate. Take output from SUM
Output. Set initial level with CH. 1 panel control. Set CH. 2 panel control full CW to generate a 10V offset. Audio starts to clip and
may become silent. If it's still audible, apply an additional positive offset with CH. 3 panel control until it is just silent. Set CH. 4
panel control to full CCW and apply envelope to Signal Input or generate envelope with CH. 4. This patch creates a VCA with
asymmetrical clipping in the waveform. It works with CV also, but be sure to adjust CV input settings to deal with the large base
offset. The INV output may be more useful in some situations.
Voltage Controlled Clock Divider
Clock signal applied to Trigger Input CH. 1 or 4 is processed by a divisor as set by Rise parameter. Increasing Rise sets divisor
higher, resulting in larger divisions. Fall time adjusts the width of the resulting clock. If the Width is adjusted to be greater than
the total time of the division, the output remains “high.”
FLIP-FLOP (1-Bit Memory)
In this patch CH. 1 Trigger Input acts as the “Set” input, and CH. 1 BOTH Control Input acts as the “Reset” Input. Apply Reset
signal to CH. 1 BOTH Control Input. Apply Gate or logic signal to CH. 1 Trigger Input. Set Rise to Full CCW, Fall to Full CW,
Vari-Response to Linear. Take “Q” output from EOC. Patch EOC to CH. 4 Signal to achieve “NOT Q” at the EOC Output. This patch
has a memory limit of about 3 minutes, after which it forgets the one thing you told it to remember.
Logic Inverter
Apply logic gate to CH. 4 Signal Input. Take output from CH. 4 EOC.
Comparator/Gate Extractor (a new take)
Send signal to be compared to CH. 2 Input. Set CH. 3 panel control into the negative range. Patch SUM out into CH. 1 Signal
Input. Set CH. 1 Rise and Fall to 0. Take output from CH. 1 EOR. Observe signal polarity with CH. 1 Unity LED. When signal goes
slightly positive, EOR trips. Use CH. 3 panel control to set the threshold. Some attenuation of CH. 2 may be necessary to find the
right range for a given signal. Use CH. 1 Fall control to make the gates longer. CH. 1 Rise control sets the length of time the
signal must be above the threshold to trip the comparator.
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Summary of Contents for MATHS
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