BLUEPIRAT RAPID | USER MANUAL/
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8
The storage concept
8.1
Architecture
To increase the recording performance, the BLUEPIRAT Rapid data logger has two internal
memory paths working parallel.
One storage path is optimized for recording raw data. This is implemented via Field Program-
mable Gate Arrays (FPGA), i.e. this path is implemented directly in hardware via a logic circuit.
This ensures the best possible recording performance. The downstream storage architecture to
the memory (SSDs) is also optimized by parallelization. The internal CPU is generally not
loaded in this process. Data of this memory path is referred to as "logic data" in this manual.
The second memory path is implemented via the internal CPU of the device. This makes it pos-
sible to support SW protocols. Examples are TCP/UDP server, camera recordings, CCP XCP
and others. The data is recorded on a single SSD. The CPU data recording is more flexible than
FPGA based recording, but the recording performance is much lower.
"Logic data" and "processor data" are strictly separated in the device. The CPU cannot access
logic data; the FPGA cannot access processor data. When the data logger is read out, the Sys-
tem Client or Download Terminal merges the data.
Figure 8.1: The storage concept of BLUEPIRAT Rapid