22
P/N: PM1576
MX25L4006E
REV. 1.6, OCT. 24, 2014
Table 7. Parameter Table (0): JEDEC Flash Parameter Tables
Description
Comment
Add (h)
(Byte)
DW Add
(Bit)
Data (h/b)
(Note1)
Data
(h)
Block/Sector Erase sizes
00: Reserved, 01: 4KB erase,
10: Reserved,
11: not support 4KB erase
30h
01:00
E5h
Write Granularity
0: 1Byte, 1: 64Byte or larger
02
Write Enable Instruction Required
for Writing to Volatile Status
Registers
0: not required
1: required 00h to be written to the
status register
03
Write Enable Opcode Select for
Writing to Volatile Status Registers
0: use 50h opcode,
1: use 06h opcode
Note: If target flash status register is
nonvolatile, then bits 3 and 4 must
be set to 00b.
04
Unused
Contains 111b and can never be
changed
07:05
4KB Erase Opcode
31h
15:08
20h
(1-1-2) Fast Read (Note2)
0=not support 1=support
32h
16
81h
Address Bytes Number used in
addressing flash array
00: 3Byte only, 01: 3 or 4Byte,
10: 4Byte only, 11: Reserved
18:17
Double Transfer Rate (DTR)
Clocking
0=not support 1=support
19
(1-2-2) Fast Read
0=not support 1=support
20
(1-4-4) Fast Read
0=not support 1=support
21
(1-1-4) Fast Read
0=not support 1=support
22
Unused
23
Unused
33h
31:24
FFh
Flash Memory Density
37h:34h 31:00
(1-4-4) Fast Read Number of Wait
states (Note3)
0 0000b: Wait states (Dummy
Clocks) not support
38h
04:00
00h
(1-4-4) Fast Read Number of
Mode Bits (Note4)
000b: Mode Bits not support
07:05
(1-4-4) Fast Read Opcode
39h
15:08
FFh
(1-1-4) Fast Read Number of Wait
states
0 0000b: Wait states (Dummy
Clocks) not support
3Ah
20:16
00h
(1-1-4) Fast Read Number of
Mode Bits
000b: Mode Bits not support
23:21
(1-1-4) Fast Read Opcode
3Bh
31:24
FFh
SFDP Table below is for
MX25L4006EM1I-12G, MX25L4006EM2I-12G, MX25L4006EPI-12G, MX25L4006EZNI-
Summary of Contents for MX25L4006E
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