27
3-6-1 DRAM Configuration
Phoenix – AwardBIOS CMOS Setup Utility
DRAM Timing Settings
Item Help
Auto Configuration Auto
DRAM CAS Latency Auto
Min RAS# active Time<Tras> Auto
Row precharge Time<Trp> Auto
RAS# to CAS# Delay<Trcd> Auto
DRAM Bank Interleaving Disabled
Memory Hole Remapping Enabled
Bottom of UMA DRAM [31:24 252
Menu Level >>
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
RAS-to-CAS Delay
This field let’s you insert a timing delay between the CAS and RAS strobe signals, used when
DRAM is written to, read from, or refreshed.
Fast
gives faster performance; and
Slow
gives
more stable performance. This field applies only when synchronous DRAM is installed in the
system. The settings are: 4T and 3T.
Row Precharge Time
If an insufficient number of cycles is allowed for the RAS to accumulate its charge before
DRAM refresh, the refresh may be incomplete and the DRAM may fail to retain date.
Fast
gives faster performance; and
Slow
gives more stable performance. This field applies only
when synchronous DRAM is installed in the system. The settings are: 2T and 3T.
DRAM CAS Latency
When synchronous DRAM is installed, the number of clock cycles of CAS latency depends
on the DRAM timing. The settings are: 2T and 2.5T.
3-6-2 VGA Settings (Option)
Phoenix – AwardBIOS CMOS Setup Utility
VGA Settings
Item Help
> Obboard VGA Device
Auto
> Onboard Share Memory 64MB
> PMU
Auto
>
RGB/TV Display
Auto
>
TV Mode Support
Auto
Menu Level >
↑↓→←
Move Enter:/-/PU/PD:Value F10:Save ESC:Exit F1:General Help
F5:Previous Values F6:Optimized Defaults F7:Standard Defaults
