M5Stack POECAM, Manual

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3 ． FUNCTIONAL DESCRIPTION
This chapter describes the ESP32-D0WDQ6-V3 various modules and functions.
1.1. CPU AND MEMORY
Xtensa®single -/dual-core32-bitLX6microprocessor(s), upto600MIPS
(200MIPSforESP32-S0WD/ESP32-U4WDH, 400 MIPS for ESP32-D2WD):
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448 KB ROM
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520 KB SRAM
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16 KB SRAM in RTC
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QSPI supports multiple flash/SRAM chips
1.2. STORAGE DESCRIPTION
1.2.1. External Flash and SRAM
ESP32 support multiple external QSPI flash and static random access memory
(SRAM), having a hardware-based AES encryption to protect the user programs and
data.
⚫
ESP32 access external QSPI Flash and SRAM by caching. Up to 16 MB external
Flash code space is mapped into the CPU, supports 8-bit, 16-bit and 32-bit
access, and can execute code.
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Up to 8 MB external Flash and SRAM mapped to the CPU data space, support
for 8-bit, 16-bit and 32-bit access. Flash supports only read operations, SRAM
supports read and write operations.
1.3. CRYSTAL
External 2 MHz ~ 60 MHz crystal oscillator (40 MHz only for Wi-Fi/BT
functionality)