R7HL-YV4L
5-2-55, Minamitsumori, Nishinari-ku, Osaka 557-0063 JAPAN
Phone: +81(6)6659-8201 Fax: +81(6)6659-8510 E-mail: [email protected]
EM-7812-AV Rev.1 P. 5 / 5
COMMUNICATION CABLE CONNECTIONS
Master Module
RXD+
RXD–
TXD+
TXD–
FG
(SHIELD)
Slave Module
RXD+
RXD–
TXD+
TXD–
FG
(SHIELD)
Slave Module
TXD+
Terminating
Resistor
TXD–
RXD+
RXD–
SHIELD
Terminating
Resistor
Master Module
TR+
TR–
FG
(SHIELD)
Slave Module
TR+
TR–
FG
(SHIELD)
Slave Module
TR+
TR–
SHIELD
Note: Be sure to turn ON the switch of the terminating resistor located at both ends of the modules.
Terminating
Resistor
Terminating
Resistor
■
MASTER CONNECTION
• Full-duplex communication
• Half-duplex communication
I/O DATA DESCRIPTIONS
■
ANALOG OUTPUT
0
15
ADD.n
0
15
CH0 – 3
Analog output data
CH designation of
analog output data
Unused
Analog output data
CH designation of
analog output data
Unused
• Di
■
ANALOG OUTPUT (R7HL-YV4L)
• Do
The data is 12-bit binary.
Divided by 4 times scan, 4 points output data is transferred by using CH designation bit.
For Di, the data written to Do is echoed back.
■
DATA ACQUISITION PROCEDURE
1) Write the desired CH designation bit (see table below) to the CH designation bit (bit 12 to 14) for the analog output data of
Do, from the host program.
2) After one scan, the channel specified above is updated.
CHANNEL
CH DESIGNATION BIT
0
000
1
001
2
010
3
011
