02001346 Rev 1
HPP-1000/6000 User Manual
Page 10 of 19
The HPP communicates with the LDD to decrease the output voltage up to 25% of the
programmed voltage in order to have good efficiency. The requirement is that the LDD
output voltage must be programmed to be higher than the expected load voltage but not
too high that the HPP cannot pull it down to have 1V at the end of the pulse. The HPP
has a “load-Match” detector circuit and will shut down if the difference between Vin and
Vout is too high (more than 10V at more than 51% rated output current). To allow the
best Vout program, the HPP will defeat this protection feature when the output current is
programmed less than 50%.
For proper voltage programming, we can set and record the input voltage as follows:
Program the output voltage to about 20% higher than the expected load voltage.
Run pulses with lower than 50% max pulse current. The input voltage will be reduced
automatically. Monitor the output current to make sure the pulse shape is correct. Reduce
the input voltage further by reducing the V-program signal on the LDD until the output
current fails to regulate at the end of the pulse. This is the minimum input voltage
required for this particular load. Now we can stop the pulser and program the LDD
output voltage about 20% higher than this minimum voltage. Make sure the HPP is OFF
(disabled) at this time.
If the voltage is so high that the HPP cannot pull it down to have 1V at the end of the
pulse, the system will be inefficient and will result in over heat and thermally shut down.
If the voltage is too high, the HPP will shut off by the “load-match” detector when the
output current is higher than 50%.
The HPP has an optional programmable simmer up to 10Amp. The simmer current is
ON when the pulse current is OFF and OFF when the pulse current is ON.
CW/Pulse mode selection: (Optional)
In some applications where the system can switch from pulse to CW, the signal
CW/Pulse can be used.
When in Pulse mode, the HPP is working as a linear regulator and puts out the pulsed
current requested at the I-program signal. This operation will require some voltage
across the linear regulator and that translate into power loss.
When in CW mode, the transistors in the linear regulator are saturated and the only loss
will be the Rds-on of the FET bank against the output current. The HPP is now acting as
a wire with the impedance of the Rds-on and the current should be controlled by the
LDD.
It is advisable that the HPP must be disabled, LDD output voltage should be programed
to lower than the load voltage and current should be programmed to minimum when
switching from pulse to CW mode.
If the output voltage is higher than the load voltage, there will be current spikes to the
load and may damage the load.
Another option is to run the HPP at 100% duty cycle. In this case, we can turn the HPP
current program to 105% and control the output current by the LDD.
