Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
Hardware Architecture April 1998
2-18
DRAFT COPY
Lucent Technologies Inc.
2.2 Core Architecture Overview
(continued)
2.2.3 X Space Address Arithmetic Unit (XAAU)
The XAAU contains registers and an adder that control the sequencing of instructions in the processor. The pro-
gram counter (PC) automatically increments through the instruction space and specifies addresses for instruction
fetches. The interrupt return register (pi) and the subroutine return register (pr) are automatically loaded with
return addresses that direct the return to main program execution from interrupt service routines and subroutines.
High-speed, register-indirect instruction/coefficient memory addressing with postincrementing is done by using the
pt register. The signed register i is used to hold a user-defined postincrement, or a fixed postincrement of +1 is
available.
The XAAU of the DSP1600 decodes the 16-bit instruction/coefficient address and produces enable signals for the
appropriate X-memory segment. The possible X segments are internal ROM, each 1 Kword bank of dual-port
RAM, and external ROM. The locations of these memory segments depend on which of the four memory maps is
selected (see
Section 3.2, Memory Space and Addressing ).
A core security mode can be selected by mask option
1
. This prevents reading out the contents of on-chip memo-
ries from off-chip.
2.2.4 Cache
Under user control, the on-chip cache memory can store instructions for repetitive operations to increase the
throughput and the coding efficiency of the device. The cache can store up to 15 instructions at a time and can
repeatedly cycle through those instructions up to 127 times without using user defined loop, test, and conditional
branch instructions. The set of instructions is executed as it is loaded into the cache, so zero-overhead looping is
achieved. The cache iterative count can be specified either as an immediate value at assembly time or can be
determined by the use of the cloop register. Instructions previously stored in the cache can be re-executed without
reloading the cache.
Note: Instructions in a cache loop are noninterruptible.
Cache instructions eliminate the overhead if repeating a block of instructions. Therefore, the cache reduces the
need to implement in-line coding in order to maximize the throughput. A routine using the cache uses fewer ROM
locations than an in-line coding of the same routine.
For two-operand multiply/arithmetic logic unit (ALU) instructions that do not require a write to memory, executing
from the cache decreases the execution time from two instruction cycles to one instruction cycle resulting in an
increase in throughput.
2.2.5 Control
The control block provides overall DSP1611/17/18/27/28/29 system coordination. Inputs are provided to the con-
trol block over the program data bus (XDB). The instructions are decoded by hardware in the control block. The
execution of the phases of an instruction is controlled by hardware throughout the DSP1611/17/18/27/28/29
device. The hardware sequences instructions through the pipeline and controls the I/O, the processing, the mem-
ory accesses, and the timing necessary to perform each operation.
1.The internal ROM memory of the DSP1611 is only available with a standard boot routine. DSP1611 devices do not offer the secure mask
option.