
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
Information Manual
Error Correction Coprocessor (DSP1618/28 Only)
April 1998
14-4
DRAFT COPY
Lucent Technologies Inc.
(continued)
14.2.1 Branch Metric Unit (continued)
Six 8-bit soft symbols S(0),
. . .
, S(5) are loaded into the ECCP. The incremental branch metrics associated with all
2
C
state transitions are calculated as indicated in
.
The received 8-bit signals S(5),
. . .
, S(0) are stored in the S5H5 through S0H0 registers. The generating polyno-
mials G(1) and G(0) are stored in the upper and lower bytes of the ZIG10 register, respectively. The generating
polynomials G(3) and G(2) are stored in the upper and lower bytes of the ZQG32 register, respectively. The gener-
ating polynomials G(5) and G(4) are stored in the upper and lower bytes of the G54 register, respectively.
14.2.2 Update Unit
The add-compare-select operation of the Viterbi algorithm is performed in this unit. At every time instant, there are
2
C
state transitions of which 2
C – 1
state transitions survive. The update unit selects and updates 2
C – 1
surviving
sequences in the traceback RAM that consists of the fourth bank of the internal RAM (RAM4). The accumulated
cost of the path p at the Jth instant (ACC(J, p)) is the sum of the incremental branch metrics belonging to the path
p up to the time instant J:
The update unit computes and stores full-precision 24-bit resolution path metrics of the bit sequence. To assist the
detection of a near overflow in the accumulated path cost, an internal vectored interrupt (EOVF) is provided.
14.2.3 Traceback Unit
The traceback unit selects a path with the smallest path metric among 2
C – 1
survivor paths at every instant. The
last signal of the path corresponding to the maximum likelihood sequence is delivered to the decoder output. The
depth of this last signal is programmable at the symbol rate. The traceback decoding starts from the minimum cost
index associated with the state with the minimum cost:
If the end state is known, the traceback decoding can be forced in the direction of the right path by writing the
desired end state into the minimum cost index register (MIDX).
Table 14-1. Incremental Branch Metrics
Distance Measure
Code Rate
16-bit Incremental Branch Metric
Euclidean
1/1
Euclidean
1/2
Manhattan
1/1
Manhattan
1/2
Manhattan
1/3 or 1/4
Manhattan
1/5 or 1/6
S 0
( )
E 0
( )
–
(
)
2
Σ
S i
( )
E i
( )
–
(
)
2
[
]
>> 1 i
0
=
1
,
,
S i
( )
E i
( )
–
[
]
<< 8 i
,
0
=
Σ
S i
( )
E i
( )
–
(
)
[
]
<< 7 i
0
=
1
,
,
Σ
S i
( )
E i
( )
–
(
)
[
]
<< 6 i
0
=
1 2 or 3
,
, , ,
Σ
S i
( )
E i
( )
–
(
)
[
]
<< 5 i
0
=
1
…
4 or 5
,
, ,
, ,
ACC J p
,
(
)
Σ
BM j p
,
(
)
j
1
=
…
J
,
,
,
=
min ACC j p
1
,
(
) …
ACC j p
2
C
1
–
,
(
)
,
,
{
}
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...