Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
JTAG Test Access Port April 1998
11-16
DRAFT COPY
Lucent Technologies Inc.
11.3 Elements of the JTAG Test Logic
(continued)
11.3.5 The Bypass Register—JBPR
The bypass register (JBPR) is a single shift register stage that is defined by the standard to bypass the boundary-
scan register of devices not targeted for test in a board environment. This reduces the board serial path and, there-
fore, reduces test time—for example, if testing the targeted device by scanning vectors into its boundary-scan reg-
ister.
The BYPASS instruction selects the JBPR to be active. The BYPASS instruction is selected by default on powerup
if no device ID register is implemented. The standard requires a zero to be loaded into the shift register during the
capture-DR state if the bypass register is selected by the current instruction. This facility is used to distinguish the
ICs on a board that do not implement a device identification register by performing a data register scan cycle after
powerup. Those devices with an ID register will produce a 32-bit pattern starting with a one (see the JIDR descrip-
tion below), and those without an ID register will produce a single zero. The bypass register does not contain a
parallel output stage because it is not required to drive any device or test logic.
11.3.6 The Device Identification Register—JIDR
The JTAG device identification register (JIDR) is a 32-bit register containing the unique hardwired ID code for the
DSP1611/17/18/27/28/29. The ID code is captured in the capture-DR state from hardwired parallel inputs and can
be shifted out during the shift-DR state. Because the JIDR register does not drive any device or test logic in paral-
lel, no parallel output stage exists in its implementation.
5-4209
Figure 11-9. The Device Identification Register, JIDR
The JTAG device identification register can be used to unambiguously determine the manufacturer of a component
and to provide other descriptive information. As shown in
Figure 11-9 , the 32 bits of the JIDR are arranged into
three fields.
CAPTURE-DR
SHIFT-DR
TCK
0 0
0
1 1
0 11 12 27 28
31
VERSION
PART NUMBER
MANUFACTURER
TDI
TDO
32-bit SHIFT REG.
TO ALL CELLS
HARDWIRED PARALLEL INPUTS