Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Parallel Host Interface (PHIF) (DSP1611/18/27/28/29 Only)
Lucent Technologies Inc.
DRAFT COPY
9-7
9.1 PHIF Operation
(continued)
9.1.5 8-Bit Transfers
Eight-bit transfers are selected by setting the PMODE bit of the phifc. The timing figures for 8-bit mode look like
one-half of the 16-bit timing figures with the exception that the interrupts PIBF and POBE are set after every
instance of PIDS/PRWN or PODS/PDS in 8-bit mode.
9.1.6 Accessing the PSTAT Register
Polling the PSTAT register (performed by holding the PSTAT high during a read) provides PHIF status externally
without requiring any extra pins. This register cannot be read or written under program control and is read only
over the PB. Its sole purpose is to be polled by an external device. The DSP itself is completely oblivious to the
fact that PSTAT has been read. The state of pdx0(IN), pdx0(OUT), and the flags are unaffected, and no internal
interrupt is generated.
Table 9-1 describes the PSTAT register. The functional timing sequence for polling the
PSTAT register is the same as for the pdx0(OUT) register shown previously.
Polling the PSTAT register yields the following information:
PIBF: If 1, the parallel input buffer (pdx0(IN)) is full. This bit has the same value as the pin by the same name.
In
Intel mode, this bit is set if PIDS latches data into pdx0(IN). In Motorola mode, this bit is set if PDS latches
data into pdx0(IN). In both cases, it is cleared when the DSP reads pdx0(IN).
POBE: If 1, the parallel output buffer (pdx0(OUT)) is empty. The definition of this pin can be inverted to be
active-low by writing a 1 to the PSOBEF field of the phifc register. This bit has the same value as the pin by the
same name. In
Intel mode, this bit is set if PODS latches data into pdx0(OUT). In Motorola mode, this bit is set
if PDS latches data into pdx0(OUT). In both cases, it is cleared when the DSP writes pdx0(OUT).
Table 9-1. The PHIF Status Register, PSTAT
Bit 7—2 1 0
Field
Zeros PIBF POBE