
Information Manual
DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Parallel I/O (DSP1617 Only)
Lucent Technologies Inc.
DRAFT COPY
8-9
8.1 PIO Operation
(continued)
8.1.4 Peripheral Mode (Host Interface)
If both PIDS and PODS are in passive mode, the PIO is operating in peripheral mode. The PIO unit is designed to
allow the user to interface the DSP as a peripheral to another processor. A variety of techniques are available from
using the PIBF and POBE flags as interrupts to an external device to polling the PSTAT register. For most applica-
tions, the PIO can be interfaced with no additional logic.
is an example of a DSP to microprocessor con-
nection.
5-4193
Figure 8-7. The DSP as a Microprocessor Peripheral
Note: If PIO is configured in passive/passive (peripheral) mode, PSEL0 equals PIBF or POBE so that PSEL0 low
indicates to the microprocessor that the DSP is ready for any access.
The pins PIBF and POBE are flags that indicate parallel input buffer full and parallel output buffer empty. They are
both active-high. The input flag works if PIDS is in passive mode and is cleared otherwise. The output flag works
if PODS is in passive mode and is cleared otherwise. An external device can take PIBF going low as an interrupt
meaning the pdx[IN] register is ready for another PIO input. Likewise, an external device can take POBE going low
to mean the output buffer is loaded with data to be read.
If both PIDS and PODS are passive signals, PSEL0 no longer selects between PIO channels. PSEL0 is now the
logical OR of the two flags PIBF and POBE. This provides another way for an external device to determine
whether the PIO is ready for an access. In peripheral mode and if PSEL0 is low, the other device is free to either
read or write the PIO. Of course, this condition does not occur until the PIO is ready for either access but it
requires the use of one less pin on the DSP and possibly fewer interrupt pins on the external device.
PSEL2
PB[7:0]
PODS
PIDS
PSEL0
DSP1617
MICROPROCESSOR
SYSTEM
EN
D[7:0]
READ
WRITE
INTREQ
8
Summary of Contents for DSP1611
Page 18: ...Chapter 1 Introduction...
Page 27: ...Chapter 2 Hardware Architecture...
Page 52: ...Chapter 3 Software Architecture...
Page 116: ...Chapter 4 Instruction Set...
Page 154: ...Chapter 5 Core Architecture...
Page 176: ...Chapter 6 External Memory Interface...
Page 208: ...Chapter 7 Serial I O...
Page 237: ...Chapter 8 Parallel I O DSP1617 Only...
Page 261: ...Chapter 9 Parallel Host Interface PHIF DSP1611 18 27 28 29 Only...
Page 275: ...Chapter 10 Bit I O Unit...
Page 284: ...Chapter 11 JTAG Test Access Port...
Page 306: ...Chapter 12 Timer...
Page 313: ...Chapter 13 Bit Manipulation Unit...
Page 325: ...Chapter 14 Error Correction Coprocessor DSP1618 28 Only...
Page 350: ...Chapter 15 Interface Guide...
Page 367: ...Appendix A Instruction Encoding...
Page 379: ...Appendix B Instruction Set Summary...
Page 381: ...aD extractz aS IM16 B 52 aD insert aS arM B 53 aD insert aS IM16 B 54 aD aS aaT B 55...
Page 437: ...Index...