Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998
Lucent Technologies Inc.
DRAFT COPY
7-1
7 Serial I/O
The two serial I/O ports (SIO1 and SIO2) on the DSP1611, DSP1617, DSP1618, DSP1627, DSP1628, and
DSP1629 devices provide serial interfaces to multiple codecs and signal processors with little, if any, external
hardware. The high-speed, double-buffered ports support back-to-back transmissions with data rates up to
25 Mbits/s for a 20 ns DSP if not in multiprocessor mode (check current data sheets for exact timing information).
Each SIO has separate control and data registers. The output buffer empty (OBE) and input buffer full (IBF) flags
facilitate the reading, writing, or both of each serial I/O port by program- or interrupt-driven I/O. There are four
selectable active clock speeds. A bit-reversal mode provides compatibility with either most significant bit (MSB)
first or least significant bit (LSB) first serial I/O formats. Up to eight DSPs can be connected in a multiprocessor
configuration without any other external devices. The serial I/O control (sioc) register and time-division multiplexed
slot (tdms) register allow various modes of operation to be selected. The serial data is read and written through
the sdx registers. The serial receive/transmit address (srta) and serial input address or protocol (saddx) registers
facilitate addressing other DSP devices in multiprocessor mode.
The second SIO unit (SIO2) is functionally identical to SIO1. The SIO2 pins are multiplexed with the PIO pins for
the DSP1617 and with the PHIF pins for the DSP1611/18/27/28/29.
Figure 7-1 shows a simplified block-level representation of the serial I/O data path. The double-buffered inputs
(ISR and sdx[IN]) and outputs (sdx[OUT] and OSR) connect to the internal data bus. Serial I/O uses a register-
based implementation. The input and output buffer registers (sdx[IN] and sdx[OUT], respectively) are used in the
user program to input and output the data through the port. Both registers are referenced in the instruction set by
the name sdx. Unlike other registers in the DSP device, writing and reading of sdx are performed on two distinct
registers. The ICK, OCK, ILD, and OLD interfaces are represented by the clock generator block. The signals con-
nected to this block are bidirectional and can be programmed via the sioc register. The IFSR block provides a flag
signal for the input buffer full signal (IBF). The multiprocessor I/O is not represented in
Figure 7-1 but is described
in Section 7.6, Multiprocessor Mode Description . The signals shown on the lower portion of Figure 7-1 are
described in Section 7.3, Serial I/O Pin Descriptions .
5-4171
Figure 7-1. Serial I/O Internal Data Path
OUTPUT DATA
SHIFT REGISTER
(OSR)
OUTPUT FLAG
SHIFT REGISTER
(OFSR)
CLOCK GENERATOR
IBF ILD DI ICK OCK DO OLD OBE
INPUT
BUFFER
sdx[IN]
OUTPUT
BUFFER
sdx[OUT]
INPUT FLAG
SHIFT REGISTER
(IFSR)
INPUT DATA
SHIFT REGISTER
(ISR)
DATA BUS