Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
External Memory Interface April 1998
6-22
DRAFT COPY
Lucent Technologies Inc.
6.4 Timing Examples
(continued)
6.4.6 Write W = 1
Figure 6-8 illustrates a single write cycle to external data memory with a wait of one. At the beginning of the cycle
(coincident with the falling edge of CKO), ERAMLO goes low enabling the external memory. Then, the address is
placed on the address bus, the data bus is 3-stated by the DSP, and RWN goes low. Halfway through the write
cycle, in this case one CKO period later, the data is placed on the data bus by the DSP. At the end of the write
cycle, ERAMLO goes high allowing the external memory to latch the data. RWN also goes high. The data is left
on the bus for another CKO period to maintain hold time for the external memory.
5-4167
Figure 6-8. Write W = 1
Sample Instructions:
mwait=0x0001 /* ERAMLO W=1 */
*r3++=a0 /* Two-cycle write with W=1, r3 points to ERAMLO */
CKO
ERAMLO
DB
RWN
WRITE CYCLE W = 1
AB
ERAMLO ADDRESS
ERAMLO DATA