Lucent Technologies DSP1611, Information Manual

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DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR Information Manual
External Memory Interface April 1998
6-18
DRAFT COPY
Lucent Technologies Inc.
6.4 Timing Examples
(continued)
6.4.2 Write, Read, Read, W = 0
Figure 6-4 illustrates a typical use of the EMI. The sequence shown is a write, read, read of the ERAMHI memory
segment. The wait-state is set to 0. The ERAMHI enable goes low at the beginning of the write cycle and stays
low throughout the read cycles. The address bus (AB) has a valid address placed on it for one period of CKO in
each cycle. At the beginning of the write cycle, the data bus (DB) is 3-stated by the DSP. Halfway through the write
cycle, DB is driven with data by the DSP. At the end of the write cycle, the DSP 3-states DB because a read cycle
follows immediately. The external memory responds to the request for a read by placing data on the DB sometime
before the end of the read cycle, and the data is latched into the DSP at the falling edge of CKO. In response to a
new address, the external memory places new data on DB in the next read cycle. Because read instructions can
be carried out in one instruction cycle, these cycles are back-to-back. If the external memory needs a clock edge
from ERAMHI to initiate each cycle, the delay feature is used to delay the leading edge one half of a CKO period.
5-4163
Figure 6-4. Write, Read, Read, W = 0
Sample Instructions for the Above Sequence:
*r0++=a0 /* Two-cycle write, r0 points to ERAMHI */
y=*r1++ /* One-cycle read, r1 points to ERAMHI */
x=*r1++ /* One-cycle read, r1 points to ERAMHI */
CKO
ERAMHI
DB
READ
ADDR VALID
READ
ADDR VALID
READ
DATA
READ
DATA
WRITE
DATA
RWN
WRITE CYCLE
W = 0
READ CYCLE
W = 0
READ CYCLE
W = 0
AB
ADDR VALID
WRITE