Lucent Technologies DSP1611, Information Manual, Page: 190 / 443

Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 External Memory Interface
Lucent Technologies Inc.
DRAFT COPY
6-13
6.2 Programmable Features
Two control registers are encoded by the user to change the operation of the EMI. All 16 bits of the mwait register
and bits 14, 11, 8—6, and 4—0 of the ioc register apply to the EMI.
Wait-states: For each of the four external memory segments, the number of wait-states from 0 to 15 can be
selected in the mwait register.
Table 6-12 shows the encoding. The duration of the external memory cycle is
(1 + w) times the period of the CKO where w is the number of wait-states. If the EXM and INT1 pins are high at
reset, the mwait register is initialized to all zeros (0 wait-states). If the EXM pin is high and INT1 is low at reset, the
mwait register is initialized to all ones (15 wait-states).
Enable delays: Any one of the memory segment enables or the DSEL
1
can be delayed by approximately one-half
a CKO period by programming the ioc register as shown in Table 6-13 . The leading edge of the enable can be
delayed to avoid a situation in which two devices can drive the data bus simultaneously.
Logic sense of DSEL: Bit 6 in the ioc register selects the logic sense of the DSEL
1
output. If one, it is active-high;
if zero, it is active-low.
Table 6-12. mwait Register
Bit 15—12 11—8 7—4 3—0
Field EROM[3:0] ERAMHI[3:0] IO[3:0] ERAMLO[3:0]
1.DSEL not available in the DSP1627/28/29.
Table 6-13. ioc Register
Bit 15 14 13 12 11 10 9 8—7 6 5 4 3—0
Field Rsrvd EXTROM CKO2 EBIOH WEROM ESIO2 SIOLBC CKO[1:0] DSELH PIOLBC DDSEL0 DENB[3:0]
ioc Field Description
EXTROM If 1 and if bit 11 is 1, pulls AB15 low to download to lower 32K of EROM.
CKO2 CKO configuration — see below
EBIOH If 1, enables high half of BIO, IOBIT[7:4], and disables VEC[3:0] from pins.
WEROM If 1, allows writing into external program (X) memory.
ESIO2 If 1, enables SIO2 and low half of BIO, and disables PIO from pins.
SIOLBC If 1, DO1 and DO2 looped back to DI1 and DI2.
CKO[1:0] CKO configuration—see below.
DSELH If 1, DSEL
†
active high.
† DSEL not available in the DSP1627/28/29.
PIOLBC
‡
‡ Not available in the DSP1627/28/29.
If 1, PB[7:0] and PODS to PIDS internally looped back.
DDSEL0 If 1, delay DSEL
†
.
DENB3 If 1, delay EROM.
DENB2 If 1, delay ERAMHI.
DENB1 If 1, delay IO.
DENB0 If 1, delay ERAMLO.