Lucent Technologies DSP1611, Information Manual

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Information Manual DSP1611/17/18/27/28/29 DIGITAL SIGNAL PROCESSOR
April 1998 Core Architecture
Lucent Technologies Inc.
DRAFT COPY
5-17
5.3 Y Address Arithmetic Unit (YAAU)
(continued)
5.3.4 Addressing Modes (continued)
A code segment for controlling the previous sequence follows. It is assumed that new data is arriving in the SIO
sdx input register at the proper time.
r0=1 /* Initialize register. */
rb=1 /* Address 1 for beginning. */
re=7 /* Address 7 for end of shift register. */
loop: /* */
*r0++=sdx /* Write to memory, increment address by 1. */
/* */
do 7 { /* Initialize cache, 7 iterations. */
y=*r0++ /* Do 7 reads from memory to y and increment address by */
/* 1 each time. */
} /* */
goto loop /*Repeat, but now pointer has advanced one position */
/*past previous start. */
Other patterns are possible by changing the read/write patterns within the loop. For example, some other patterns
are: write newer data word—read older data word (simple serial delay line) and write newer data word—read older
data words from newest to oldest. The length of the virtual-shift register is limited only by the size of the selected
memory up to the 64K addressing capability of the registers. Any nonzero value written to re will enable the virtual-
shift register mode for all of the pointer registers r0—r3. Register re is cleared on reset.
5.4 Cache and Control
This portion of the core controls the instruction sequencing. It handles vectored interrupts and traps, contains a
15-word instruction cache memory, and provides decoding for registers outside of the DSP1600 core. It stretches
the processor cycle if wait-states are required (wait-states can be programmed for external memory access via the
mwait register). It also sequences downloading of self-test programs via JTAG to on-chip dual-port RAM.
5.4.1 Cache
Under user control, the on-chip cache memory stores repetitive operations to increase the throughput and the cod-
ing efficiency of the device. Use of the cache also reduces power dissipation by eliminating program memory
accesses. The cache can store up to 15 instructions at a time and then repeatedly cycle through those instructions
up to 127 times without having to use loop, test, and conditional branch instructions. The set of instructions is exe-
cuted as each instruction is loaded into the cache to achieve low overhead looping. The cache iterative count can
be specified either as an immediate value at assembly time or can be set by writing the cloop register during pro-
gram execution. Instructions previously stored in the cache can be re-executed without reloading the cache by
using the redo instruction.
Cache instructions eliminate the overhead when repeating a block of instructions. Therefore, the cache reduces
the need to implement in-line coding in order to maximize the throughput. A routine utilizing the cache uses less
ROM locations than in-line coding of the same routine.
For multiply/ALU instructions that require two reads to dual-port RAM, executing from the cache decreases the
execution time from two instruction cycles to one instruction cycle resulting in an increase in throughput.