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LSI Symbios SYM53C040, Technical Manual

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8-10

System Registers

Register: 0xFF0B

Multipurpose I/O Bank 0 Latch Mask (MPLM0)
Read/Write

MPLM0_[7:0] Multipurpose I/O Bank 0 Latch Mask

[7:0]

These read/write register bits define the write mask for
the

Multipurpose I/O Bank 0 Latch (MPL0)

register

(

0xFF0C

). A value of 1 in any of these bits allows the

corresponding bit in the MPL0 to be modified.

Register: 0xFF0C

Multipurpose I/O Bank 0 Latch (MPL0)
Read/Write

MPL0_[7:0]

Multipurpose I/O Bank 0 Latch

[7:0]

These read/write register bits store the power-on value of
the I/O pins MPIO0_0, MPIO0_1, MPIO0_2, MPIO0_3,
MPIO0_4, MPIO0_5, MPIO0_6, and MPIO0_7. The
values on these pins are latched into this register on the
deasserting edge of the RESET/ input signal or the
internal power-on reset.

7

6

5

4

3

2

1

0

MPLM0_7 MPLM0_6 MPLM0_5 MPLM0_4 MPLM0_3 MPLM0_2 MPLM0_1 MPLM0_0

Defaults:

1

1

1

1

1

1

1

1

7

6

5

4

3

2

1

0

MPL0_7

MPL0_6

MPL0_5

MPL0_4

MPL0_3

MPL0_2

MPL0_1

MPL0_0

Defaults:

x

x

x

x

x

x

x

x

Summary of Contents for Symbios SYM53C040

Page 1: ...Symbios SYM53C040 Enclosure Services Processor Order Number S14042 Technical Manual February 2000 Version 2 5...

Page 2: ...d by an update To receive product literature visit us at http www lsilogic com LSI Logic Corporation reserves the right to make changes to any products herein at any time without notice LSI Logic does...

Page 3: ...1 5 16 Kbytes SRAM 2 4 2 1 6 DMA Function 2 4 2 2 Memory Map 2 4 2 3 SCSI Core Operation 2 5 2 3 1 Recommended Use of SCSI High ID Pins 2 5 2 3 2 LVD Link Technology 2 8 2 3 3 Programmed I O Transfers...

Page 4: ...SI Interrupts 2 29 2 10 3 SFF 8067 Interrupts 2 31 2 10 4 Two Wire Serial Interrupts 2 31 2 10 5 Masking and Enabling Interrupts 2 32 2 10 6 Polling and Hardware Interrupts 2 32 2 10 7 Interrupt Servi...

Page 5: ...ter Access 9 12 9 6 Two Wire Serial Timings 9 13 9 7 SFF 8067 Interface Timings 9 14 9 8 SCSI Timings 9 16 9 8 1 Initiator Asynchronous Send 9 16 9 8 2 Initiator Asynchronous Receive 9 17 9 8 3 Target...

Page 6: ...ew 5 1 6 1 Register Set Overview 6 1 7 1 Register Set Overview 7 1 8 1 Register Set Overview 8 1 9 1 LVD Driver 9 3 9 2 LVD Receiver 9 4 9 3 SYM53C040 Clock Waveforms 9 7 9 4 Reset Waveforms 9 8 9 5 E...

Page 7: ...gnments for SFF 8067 Mode 3 18 4 1 SCSI and DMA Registers 4 2 4 2 SCSI Phase Bit Values 4 9 5 1 SFF 8067 Interface Registers 5 2 6 1 Two Wire Serial Registers 6 2 7 1 Miscellaneous Registers 7 2 7 3 P...

Page 8: ...PIO2 7 0 MPIO3 3 0 9 6 9 11 Bidirectional Signals MPLED0 7 0 MPLED1 7 0 MPLED2 7 0 9 6 9 12 SYM53C040 Clock Timings 9 7 9 13 Reset Timings 9 8 9 14 External Memory Interface Timings 9 9 9 15 External...

Page 9: ...ation It is intended for system designers who are using this device to manage SCSI or Fibre Channel peripheral device enclosures Organization This document has the following chapters and appendix Chap...

Page 10: ...397 7956 outside U S FAX 303 397 2740 Ask for document number X3 131 1994 SCSI 2 X3 253 SCSI 3 Parallel Interface or NCITS 305 199x SCSI 3 Enclosure Services SES Specification working draft SCSI Acce...

Page 11: ...ed The word assert means to drive a signal true or active The word deassert means to drive a signal false or inactive Signals that are active LOW end in a Hexadecimal numbers are indicated by the pref...

Page 12: ...xii Preface...

Page 13: ...nclosures SAF TE and SCSI 3 Enclosure Services SES enclosure specifications The enclosure monitoring services in the SYM53C040 allow a single chip solution for monitoring disk drives power supplies co...

Page 14: ...tem tasks The SYM53C040 supports Low Voltage Differential LVD access as well as Single Ended SE SCSI access without the need for external transceivers Figure 1 1 shows a typical SCSI enclosure impleme...

Page 15: ...this information to the Fibre Channel host controller and generates control outputs to control system components in response to host commands Figure 1 2 shows a typical Fibre Channel enclosure design...

Page 16: ...al to the microcontroller Downloadable upgradable firmware On chip SE and LVD SCSI transceivers for direct attach to either LVD or SE SCSI bus 16 Kbytes of onboard static RAM Two multimaster two wire...

Page 17: ...l description of each item The remainder of the chapter describes these functional areas in more detail Section 2 1 Functional Blocks Section 2 2 Memory Map Section 2 3 SCSI Core Operation Section 2 4...

Page 18: ...exed I O Register Set Accessible by Firmware Only DMA Function SYM53C80 Based SCSI Control Logic SFF8067 Mode Control Logic Mux Microcontroller Address Data Bus External RAM or ROM Optional SE or LVD...

Page 19: ...56 bytes of internal scratch RAM This microcontroller uses a shared address data bus and can address either 64 Kbytes of shared program and data memory or 16 Kbytes of internal memory and 47 Kbytes ea...

Page 20: ...g the Two Wire Serial interface Note The external parallel ROM must not be mapped into the first 16 Kbytes or the last 1 Kbyte of the external memory 2 1 6 DMA Function The DMA block provides memory a...

Page 21: ...tor and target operation arbitration and interrupts to the microcontroller The core is controlled by several registers that are described in Chapter 4 2 3 1 Recommended Use of SCSI High ID Pins The SC...

Page 22: ...nitor the value of the SHID 2 0 pins by reading the SHID 2 0 bits in the Current SCSI Data High CSDHI register 0xFC08 The Select Enable High SENHI register allows a bit to be set that corresponds to t...

Page 23: ...t SEL Bit 0xFC01 Bit 2 Wait 1 2 s Min Bus Clear Settle Set Target Mode Bit 0xFC02 Bit 6 Set TE 0xFC03 Bit 1 Set Assert I_O Bit 0xFC03 Bit 0 Write Target and Initiator s ID Bits to Output Reg Reg 0xFC0...

Page 24: ...The LSI Logic LVD Link transceivers operate in LVD and SE modes The SYM53C040 automatically detects which type of signal is connected based on voltage detected by the DIFFSENS pin The RBIAS and RBIAS...

Page 25: ...nd the Assert REQ bit 0xFC03 bit 3 is set The microcontroller must then wait for the REQ bit 0xFC04 bit 5 to become active Once REQ goes active the Phase Match bit 0xFC05 bit 3 is checked and the Asse...

Page 26: ...Send Set Transfer Memory Counter in Write Data to Reg 0xFC00 Output Data Reg Target Send Only Set Assert Data Reg 0xFC01 Bit 0 Bus Bit Target Send Only Set Assert 0xFC03 Bit 3 REQ Bit Reset Assert 0xF...

Page 27: ...e bit 0 TIP position 3 The firmware sets bit 0 in register 0x87 of the microcontroller core to place the core in idle mode 4 The DMA waits for the microcontroller to enter the idle mode before taking...

Page 28: ...FC03 Bits 2 0 Set ADB Bit Reg 0xFC01 Bit 0 Write to DMA Send Register 0xFC05 Write to Start DMA Target Receive Register 0xFC06 Set Bit 1 in Register 0x87 of the Microprocessor Core to Put It into Powe...

Page 29: ...and the address register incremented Note The entire address which is a combination of two byte wide registers will be incremented This cycle repeats until the transfer length is zero which indicates...

Page 30: ...more information on the operation of the microcontroller core refer to documentation on the Intel MCS 51 embedded microcontroller family The microcontroller core has two external interrupt functions a...

Page 31: ...means to gather external system information The Two Wire Serial interface supported by the SYM53C040 is compliant with the I2 C bus defined by Philips Electronics Figure 2 8 illustrates serial bus ac...

Page 32: ...and A8 These options are summarized in Table 2 4 The initial download attempt can also be skipped if no pull up resistor is used on signal pin AD5 Signal pin A11 indicates which serial interface will...

Page 33: ...is the number of bytes of code not including the two bytes of destination address or the two bytes of firmware length The length does include the final checksum byte The minimum firmware length is thr...

Page 34: ...there was a difference between the calculated checksum and the last byte read in at download 2 6 5 Manually Accessing External Two Wire Serial Devices The SYM53C040 Two Wire Serial interface allows t...

Page 35: ...ta Register Yes Interrupt Service Routine No Read Byte From Control Status Register Read Byte From Control Status Register PIN Bit 0 Yes No Stop Detected STS 1 Read Data From Data Register End Receive...

Page 36: ...ocations given are for 2 wire serial port 0 Two wire serial port 1 transfers operate in similar fashion Clear ACK Bit In Control Register No One Byte Left No Yes Read Data From Data Register 0xFD00 No...

Page 37: ...tial automatic jump configurable by external pull up resistors on the AD0 and AD1 pins The states of these pins are checked on chip reset In the SYM53C040 the AD0 and AD1 signal pins have internal pul...

Page 38: ...d the microcontroller will hold off from fetching its first instruction until the download completes The initial ROM download will be skipped if no external pull up is used on the AD5 signal pin the p...

Page 39: ...rns the Two Wire Serial port and the SCSI or SFF 8067 interfaces to idle states A power on reset is caused when power to the chip has been turned off and is turned back on Manually asserting the RESET...

Page 40: ...can be controlled either manually by the microcontroller through direct control of the interface pins or automatically by the SFF 8067 interface control logic which has the ability to interrupt the m...

Page 41: ...nnel device The write interrupt notifies the microcontroller that the Fibre Channel device has written a byte of data to the interface The microcontroller responds by clearing the interrupt and readin...

Page 42: ...CL_ACK Asserted Write RDATA Register DSK_RD Asserted ENCL_ACK Deasserted DSK_RD Deasserted ENCL_ACK Asserted D 3 0 RDATA 3 0 ENCL_ACK Deasserted WRF Bit 1 0xFC22 Bit 1 WDATA 3 0 D 3 0 ENCL_ACK Asserte...

Page 43: ...the SYM53C040 to quickly determine the source of an interrupt The Interrupt Mask IMR register 0xFE0D allows the corresponding interrupts in the ISR to be masked by writing a 0 to the bit location All...

Page 44: ...m being sent to the microcontroller 0xFE0E Interrupt Destination The bits in this register can be set or cleared to route interrupts to either of the two interrupt sources to the microcontroller core...

Page 45: ...y be disabled by resetting the appropriate bits in the Mode MR register 0xFC02 or the Select Enable SER register 0xFC04 When an interrupt occurs the Bus and Status BSR register and the Current SCSI Bu...

Page 46: ...An interrupt is generated for a received parity error if the Enable Parity Check bit bit 5 and the Enable Parity Interrupt bit bit 4 are set in the Mode MR register 0xFC02 Parity is checked during a r...

Page 47: ...r core should respond by clearing the interrupt and writing one byte of data to the RDATA register which is transferred to the requesting drive The write interrupt notifies the SYM53C040 that the driv...

Page 48: ...ption to this recommendation would be SCSI and 8067 interrupts since the bus speeds and the need to complete transfers quickly suggest that interrupts should be enabled 2 10 6 Polling and Hardware Int...

Page 49: ...status bits 5 Two wire serial port 1 Status 0xFD03 Contains PIN bit plus other status bits 4 DMA core DMAI 0xFC14 Enables DMA interrupt 3 2 Timer 2 Timer 1 T2C 0xFE09 Programs Timer 2 and enables an...

Page 50: ...can accept all required boundary scan instructions as well as the optional CLAMP HIGH Z and IDCODE instructions The SYM53C040 uses an 8 bit instruction register to support all boundary scan instructi...

Page 51: ...SYM53C040 Table 3 1 through Table 3 4 show a alphabetical listing and numerical listing for each version and Figure 3 3 is the functional signal grouping The pin definitions are presented in Table 3 5...

Page 52: ...11 110 109 108 107 106 105 104 103 102 101 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 SYM53C040 160 Pin QFP Top View RD VDD_CORE WR CLK_SEL VSS_CORE TESTIN VDD_IO RESET CLK TRST SDA1...

Page 53: ..._7 32 MPIO1_0 44 MPIO1_1 45 MPIO1_2 46 MPIO1_3 47 MPIO1_4 48 MPIO1_5 49 MPIO1_6 51 MPIO1_7 52 MPIO2_0 63 MPIO2_1 64 MPIO2_2 66 MPIO2_3 67 MPIO2_4 69 MPIO2_5 70 MPIO2_6 72 MPIO2_7 73 MPIO3_0 84 MPIO3_1...

Page 54: ...33 VSS_IO 34 MPLED0_0 35 MPLED0_1 36 MPLED0_2 37 MPLED0_3 38 VSS_IO 39 MPLED0_4 40 MPLED0_5 41 MPLED0_6 42 MPLED0_7 43 VDD_IO 44 MPIO1_0 45 MPIO1_1 46 MPIO1_2 47 MPIO1_3 48 MPIO1_4 49 MPIO1_5 50 VSS_...

Page 55: ...0 G11 G12 G13 AD1 AD2 AD3 AD0 SCL0 VSS_IO VSS_IO VSS_IO SIO SIO SHID1 SHID0 SHID0 H1 H2 H3 H4 H5 H6 H7 H8 H9 H10 H11 H12 H13 VDD_IO SDA0 MPIO0_0 MPIO0_1 MPIO0_2 MPIO0_6 VSS_IO MPIO2_6 SHID1 TDI DIFFSE...

Page 56: ...D4 VDD_CORE D5 TESTIN D6 SD0 D7 SD2 D8 SD6 D9 SDP0 D10 SBSY D11 SACK D12 SRST D13 SRST E1 ALE E2 PSEN E3 A15 E4 A13 E5 A9 E6 VDD_SCSI E7 SD2 E8 SD4 E9 RBIAS E10 VDD_SCSI E11 SMSG E12 SSEL E13 SSEL F1...

Page 57: ...8 MPIO2_2 L8 MPIO2_3 K8 MPIO2_4 N9 MPIO2_5 M9 MPIO2_6 H8 MPIO2_7 N10 MPIO3_0 L13 MPIO3_1 K11 MPIO3_2 K12 MPIO3_3 J10 MPLED0_0 K2 MPLED0_1 J4 MPLED0_2 L1 MPLED0_3 K3 MPLED0_4 L2 MPLED0_5 K4 MPLED0_6 L3...

Page 58: ...IFFSENS SHID 2 0 SHID 2 0 RBIAS RBIAS MPIO0 7 0 MPIO1 7 0 MPIO2 7 0 MPIO3 3 0 MPLED0 7 0 MPLED1 7 0 MPLED2 7 0 SYM53C040 160 Pin QFP or 169 Ball BGA SCL0 SDA0 SCL1 SDA1 TCK TMS TDI TDO TRST AD 7 0 A 1...

Page 59: ...the 2 wire serial interface 1 If no external pull up is used the download will use the 2 wire serial interface 0 A 10 8 are used to select a chip address for the serial ROM For more information on th...

Page 60: ...ain bidirectional None external pull up required SDA0 SDA1 23 150 H2 B5 Two Wire Serial Port 0 Data Two Wire Serial Port 1 Data 2 mA 5 V tolerant TTL Schmitt open drain bidirectional None external pul...

Page 61: ...N6 M6 L6 Open drain multipurpose LED bank 1 outputs Any unused LED outputs must be tied to VSS HIGH 16 mA 5 V tolerant TTL open drain bidirectional None MPLED 2_ 7 0 82 81 80 79 78 77 75 74 J9 L11 K1...

Page 62: ...hip If the SYM53C040 watchdog timer is used and it expires it can force an internal chip reset and assert the RESET pin LOW to reset external devices if bit 7 in register 0xFF05 is set 4 mA open drain...

Page 63: ...2 pin is the SE signal pin and the SHID2 pin should be connected as a virtual ground on the SCSI connector SE or LVD SCSI I O None SHID1 SHID1 96 97 H9 G11 SCSI High ID 1 This LVD SCSI pair may be con...

Page 64: ...ual ground on the SCSI connector SE or LVD SCSI I O None SMSG SMSG 111 112 E11 F8 SCSI MSG signal In SE mode the SMSG pin is the SE signal pin and the SMSG pin should be connected as a virtual ground...

Page 65: ...SE mode the SDP0 pin is the SE signal pin and the SDP0 pin should be connected as a virtual ground on the SCSI connector SE or LVD SCSI I O None SD7 SD7 SD6 SD6 SD5 SD5 SD4 SD4 SD3 SD3 SD2 SD2 SD1 SD...

Page 66: ...ignal to control the JTAG test operations and boundary scans 5 V tolerant TTL input 100 A pull up TDI 92 H10 Test Data In The Test Data In pin receives serial input data and commands for JTAG test ope...

Page 67: ...G7 G8 H7 VSS supply for I O signal pins Must be connected to ground VSS VDD_IO 12 24 43 71 88 154 B4 F4 H1 K13 L9 N3 VDD supply for I O signal pins Must be connected to 3 3 V power supply VDD VSS_ SC...

Page 68: ...L_1 146 C6 When PARALLEL_ESI is asserted this signal contains bit 1 of a data nibble for read and write operations When PARALLEL_ESI is deasserted this signal is the SEL_1 signal included for compatib...

Page 69: ...evice is ready to write data When PARALLEL_ESI is deasserted this signal is the SEL_6 signal included for compatibility with SFF 8045 Port 0 4 mA open drain bidirectional PARALLEL_ ESI 139 B7 Used to...

Page 70: ...ions When PARALLEL_ESI is deasserted this signal is the SEL_3 signal included for compatibility with SFF 8045 Port 1 4 mA open drain bidirectional ENCL_ACK SEL_4 132 D8 When PARALLEL_ESI is asserted t...

Page 71: ...e state of the protocol Port 1 4 mA open drain bidirectional PA0 127 D9 This pin contains bit 0 of the physical address of the enclosure Port 0 Input PA1 126 B10 This pin contains bit 1 of the physica...

Page 72: ...it 4 of the physical address of the enclosure Port 1 Input PA5 106 F10 This pin contains bit 5 of the physical address of the enclosure Port 1 Input PA6 104 F13 This pin contains bit 6 of the physical...

Page 73: ...y zero Any bits marked as reserved should always be written to zero mask all information read from them Reserved bit functions may change at any time Unless otherwise indicated all bits in registers a...

Page 74: ...tatus CSBS Read Select Enable SER Write 0xFC04 Bus and Status BSR Read DMA Send DSR Write 0xFC05 Start DMA Target Receive SDTR 0xFC06 Reset Parity Interrupt RPI Read Start DMA Initiator Receive SDIR W...

Page 75: ...tion to check for higher priority arbitrating devices Parity is not guaranteed valid during arbitration Register 0xFC00 Output Data ODR Write Only DB 7 0 SCSI Output Data 7 0 The Output Data register...

Page 76: ...It indicates that a bus free condition has been detected and that the chip has asserted BSY and the contents of the Output Data ODR register 0xFC00 onto the SCSI bus The AIP bit will remain active un...

Page 77: ...e ATN is normally asserted by the initiator to request a Message Out bus phase Note that since Assert SEL and Assert ATN are in the same register a select with ATN may be implemented with one MPU writ...

Page 78: ...target device bit set to 1 In order for the signals ATN and ACK to be asserted on the SCSI bus the Target Mode bit must be reset 0 In order for the signals C_D I_O MSG and REQ to be asserted on the SC...

Page 79: ...set to 1 for all DMA send operations In the DMA mode REQ and ACK are automatically controlled The DMA Mode bit is not reset at the end of a DMA transfer DMA mode must be turned off by writing a 0 int...

Page 80: ...rt C_D and Assert MSG bits must match the corresponding bits in the Current SCSI Bus Status CSBS register 0xFC04 The Assert REQ bit bit 3 has no meaning when the SYM53C040 is operating as an initiator...

Page 81: ...for pending data transfers The SCSI bus status information in this register may also help determine why a particular interrupt occurred RST SCSI Reset 7 BSY Busy 6 REQ Request 5 MSG Message 4 C_D Comm...

Page 82: ...gister 0xFC0C If the Enable Parity Checking bit register 0xFC02 bit 5 is active 1 parity will be checked during selection Register 0xFC05 Bus and Status BSR Read Only The Bus and Status register is a...

Page 83: ...07 PMATCH Phase Match 3 The SCSI signals MSG C_D and I_O represent the current information transfer phase The Phase Match bit indicates whether the current SCSI bus phase matches the lower three bits...

Page 84: ...e from the SCSI bus to the DMA core for target operation only The DMA Mode bit register 0xFC02 bit 1 and the Target Mode bit register 0xFC02 bit 6 must both be set prior to writing this register Regis...

Page 85: ...t Enable High SENHI Write Only SHID 2 0 SCSI High ID 7 5 The Select Enable Register High for the SCSI High ID lines is a write only register that is used as a mask to monitor a single ID during a sele...

Page 86: ...apability for handling SCSI protocol so all phase changes and error conditions must still be handled manually by the microcontroller The DMA direction is based solely on the SCSI I O phase lines R Res...

Page 87: ...this bit is 0 the other status bits in this register will be valid and the DTL register will hold the remaining transfer count Conditions for which the SCSI core will interrupt are discussed in Chapt...

Page 88: ...nterrupted transfer resumes Register 0xFC13 DMA Source Destination High DSDH Read Write DSDH 7 0 DMA Source Destination High 7 0 These register bits store the most significant byte of the DMA function...

Page 89: ...rrupt DMAI Read Write R Reserved 7 1 INT DMA Interrupt 0 This register bit is the interrupt value for the DMA This interrupt will only be enabled if the IEN bit in the DMA Status register is set 7 1 0...

Page 90: ...4 18 SCSI and DMA Registers...

Page 91: ...nary zero Any bits marked as reserved should always be written to zero mask all information read from them Reserved bit functions may change at any time Unless otherwise indicated all bits in register...

Page 92: ...locations are separated by a slash with the port 0 address listed first Table 5 1 the register map summarizes the SFF 8067 registers in graphical form Table 5 1 SFF 8067 Interface Registers 31 16 15...

Page 93: ...t contain data which is transferred in on the associated 8067 port in response to a write request at that port Register 0xFC22 0xFC2A Port Control Status PCST0 PCST1 Read Write PME Port Manual Enable...

Page 94: ...ister This bit is cleared by the associated 8067 port when the register data has been transferred onto the associated 8067 port and acknowledged WRF Write Register Full read only 2 This bit is written...

Page 95: ...registers are read only registers that contain values of the PA inputs Register 0xFC24 0xFC2C Live ESI LESI0 LESI1 Read Only PESI PARALLEL_ESI Value 7 Reading this active low bit gives the state of t...

Page 96: ...f the PA4 signal D 3 0 8067 Interface Data Nibble Bits 3 0 Reading these bits gives the contents of the D 3 0 signals on the SFF 8067 interface If PESI is 1 these bits reflect the value of the PA 3 0...

Page 97: ...low bit is cleared the drive is ready to read data from the SYM53C040 ACK ENCL_ACK Value 4 This active low bit is cleared as an acknowledge signal driven by the SYM53C040 in discovery read and write...

Page 98: ...5 8 SFF 8067 Registers...

Page 99: ...to bits that are programmed to binary zero Any bits marked as reserved should always be written to zero mask all information read from them Unless otherwise indicated all bits in registers are active...

Page 100: ...rface 0 address listed first Table 6 1 the register map summarizes the Two Wire Serial registers in graphical form Table 6 1 Two Wire Serial Registers 31 16 15 0 ES 0 2 Definition Address Two Wire Ser...

Page 101: ...lave address This register should be programmed even if slave mode is not supported by the firmware If this register is not programmed to a value other than zero then the interface will be in a monito...

Page 102: ...uld be for D1 to be 128 and D0 to be 4 The value written into the register would be 0x16 This would yield a 78 125 kHz SCL output clock speed Register 0xFD00 0xFD02 Data ES0 ES1 ES2 100 Read Write D 7...

Page 103: ...communication with the serial shift register S0 and status register S1 are accessible ES 1 2 Register Selection Bits 5 4 These bits select the Two Wire Serial register that is read written by accessi...

Page 104: ...nterface ACK Acknowledge 0 When set this bit will enable an ACK to be transmitted during the ninth clock cycle of the transfer after receiving a data byte Register 0xFD01 0xFD03 Control Register Reads...

Page 105: ...t masked in the Interrupt Mask IMR register STA Start 2 When set this bit signifies that the byte located in the Data register 0xFD00 0xFD02 ES0 ES1 ES2 100 will be sent out on the Two Wire Serial bus...

Page 106: ...the SYM53C040 i e Misplaced Start or Stop Setting this bit clears the BB_N bit and resets the PIN bit LRB AD0 Last Received Bit Address 0 Bit 3 This bit specifies one of the following depending on th...

Page 107: ...ve on the Data register interface requesting the exact same operation then the two masters will not observe each other and a parallel operation has occurred BB_N Bus Busy 0 When active logic 0 this ac...

Page 108: ...2 When the CTL1 bit is low this bit will be the value output on the SDA1 pin SCLO1 ITF1 SCL Output 1 When the CTL1 bit is low this bit will be the value output on the SCL1 pin CTL1 ITF1 Control 0 Whe...

Page 109: ...TL0 bit is low this bit will be the value output on the SDA0 pin SCLO0 ITF0 SCL Output 1 When the CTL0 bit is low this bit will be the value output on the SCL0 pin CTL0 ITF0 Control 0 When this bit is...

Page 110: ...6 12 Two Wire Serial Registers...

Page 111: ...inary zero Any bits marked as reserved should always be written to zero mask all information read from them Reserved bit functions may be changed at any time Unless otherwise indicated all bits in reg...

Page 112: ...xFE01 Watchdog Final Chain WDFC 0xFE02 Miscellaneous Control MCR 0xFE03 Interrupt Status ISR 0xFE04 Timer 1 Control T1C 0xFE05 Timer 1 Threshold T1TH 0xFE06 Timer 1 Secondary Chain T1SC 0xFE07 Timer 1...

Page 113: ...factor of 4000 yielding a 10 kHz clock to the secondary chain when the internal system clock is 40 MHz The secondary chain divides the primary chain output by a factor of 100 yielding a 100 Hz clock T...

Page 114: ...HR3 WTHR2 WTHR1 WTHR0 Time out Value 0 0 0 0 Timer disable 0 0 0 1 10 ms 0 0 1 0 20 ms 0 0 1 1 30 ms 0 1 0 0 40 ms 0 1 0 1 50 ms 0 1 1 0 60 ms 0 1 1 1 70 ms 1 0 0 0 80 ms 1 0 0 1 90 ms 1 0 1 0 100 ms...

Page 115: ...values in this register are not affected by a soft reset R Reserved 7 4 WDFC 3 0 Watchdog Final Chain 3 0 These register bits provide the ability to read the 4 bit value in the final watchdog timer d...

Page 116: ...ion when not in LVD mode SISO SCSI Isolation 2 When set this bit 3 states and logically disconnects the SYM53C040 SCSI port from the SCSI bus when in SE mode DIFFSENS VSS TE TolerANT Enable 1 This bit...

Page 117: ...Interface 0 Interrupt read only 5 A value of 1 in this bit indicates an interrupt pending from the two wire serial port_0 block The bit goes to 0 when the interrupt is cleared from the two wire serial...

Page 118: ...hat run independently of the microcontroller core Each timer can be programmed to generate one of the two possible interrupts to the microcontroller core as long as these interrupts are not masked in...

Page 119: ...d 3 1 T1IEN Timer 1 Interrupt Enable read only 0 A value of 1 in the T1IEN bit enables the timer to interrupt the microcontroller core when the timer expires This bit is cleared upon chip reset Regist...

Page 120: ...in T1FC Read Only T1FC 7 0 Timer 1 Final Chain 7 0 These register bits provide the ability to read the final timer 1 divider chain The timer expires when the value of this divider chain is equal to th...

Page 121: ...e timer to advance beyond the clear state T2PS Timer 2 Prescaler 4 A value of 1 in the T2PS bit selects the additional divide by 100 secondary divider chain yielding a timer range of 0 5 ms to 128 ms...

Page 122: ...value of 256 times the selected timer resolution Register 0xFE0B Timer 2 Secondary Chain T2SC Read Only R Reserved 7 T2SC 6 0 Timer 2 Secondary Chain 6 0 These register bits provide the ability to re...

Page 123: ...the T2IEN bit 0xFE09 bit 0 is set Register 0xFE0D Interrupt Mask IMR Read Write These register bits provide the ability to mask the corresponding interrupts in the Interrupt Status ISR register 0xFE0...

Page 124: ...r 2 Interrupt 3 Clearing this bit masks this interrupt Setting this bit enables the interrupt IMR2 Timer 1 Interrupt 2 Clearing this bit masks this interrupt Setting this bit enables the interrupt IMR...

Page 125: ...o the external interrupt 1 input of the microcontroller and a value of 0 written to a given bit will route the corresponding interrupt of the ISR register to the external interrupt 0 input of the micr...

Page 126: ...7 16 Miscellaneous Registers...

Page 127: ...ny bits marked as reserved should always be written to zero mask all information read from them Reserved bit functions may be changed at any time Unless otherwise indicated all bits in registers are a...

Page 128: ...ose I O Bank 1 Input MPI1 0xFF12 Multipurpose I O Bank 1 Latch Mask MPLM1 0xFF13 Multipurpose I O Bank 1 Latch MPL1 0xFF14 Multipurpose I O Bank 1 Pull down Enable MPPE1 0xFF15 Reserved 0xFF16 0xFF17...

Page 129: ...MLI1H 0xFF3B Multipurpose LED Bank 1L Latch Mask MLLM1L 0xFF3C Multipurpose LED Bank 1H Latch Mask MLLM1H 0xFF3D Multipurpose LED Bank 1L Latch MLL1L 0xFF3E Multipurpose LED Bank 1H Latch MLL1H 0xFF3...

Page 130: ...stor if no external pull up resistor is used the reset value will be 0 do not perform serial ROM download If an external pull up resistor is used the reset value will be 1 perform serial ROM download...

Page 131: ...if no external pull up resistor is used the reset value is 0 and the first microcontroller instruction will be fetched from address 0x0000 If an external pull up resistor is used the reset value is 1...

Page 132: ...t value of this bit matches the TTL voltage level on the A11 pin at reset A value of 0 selects two wire serial port 0 a value of 1 selects two wire serial port 1 DLADR 2 0 Download ROM Address 2 0 The...

Page 133: ...tchdog time out reset to be driven on the external reset pin This bit is not affected by a soft reset Table 8 3 Fast LED Blink Rates 40 MHz Internal Clock FBR1 FBR0 Fast Blink Rate Fast Blink Period 0...

Page 134: ...s set to a 1 the MPIO3_0 pin is mapped to the INT0 external interrupt function of the microcontroller core and the MPIO3_1 pin is mapped to the INT1 external interrupt function of the microcontroller...

Page 135: ...ed at power up These pins also have internal 100 A pull down resistors which can be disabled with the Multipurpose I O Bank 3 Pull down Enable MPPE3 register 0xFF25 Register 0xFF0A Multipurpose I O Ba...

Page 136: ...purpose I O Bank 0 Latch MPL0 Read Write MPL0_ 7 0 Multipurpose I O Bank 0 Latch 7 0 These read write register bits store the power on value of the I O pins MPIO0_0 MPIO0_1 MPIO0_2 MPIO0_3 MPIO0_4 MPI...

Page 137: ...0 indicates the pull down is inactive Register 0xFF10 Multipurpose I O Bank 1 Output MPO1 Read Write MPO1_ 7 0 Multipurpose I O Bank 1 Output 7 0 The values stored in these register bits are driven on...

Page 138: ...stated at power up These pins also have internal 100 A pull down resistors which can be disabled with the Multipurpose I O Bank 3 Pull down Enable MPPE3 register 0xFF25 Register 0xFF12 Multipurpose I...

Page 139: ...O Bank 1 Latch MPL1 Read Write MPL1_ 7 0 Multipurpose I O Bank 1 Latch 7 0 These read write register bits store the power on value of the I O pins MPIO1_0 MPIO1_1 MPIO1_2 MPIO1_3 MPIO1_4 MPIO1_5 MPIO...

Page 140: ...alue of 0 indicates the pull down is inactive Register 0xFF18 Multipurpose I O Bank 2 Output MPO2 Read Write MPO2_ 7 0 Multipurpose I O Bank 2 Output 7 0 The values stored in these register bits are d...

Page 141: ...t power up These pins also have internal 100 A pull down resistors which can be disabled with the Multipurpose I O Bank 3 Pull down Enable MPPE3 register 0xFF25 Register 0xFF1A Multipurpose I O Bank 2...

Page 142: ...purpose I O Bank 2 Latch MPL2 Read Write MPL2_ 7 0 Multipurpose I O Bank 2 Latch 7 0 These read write register bits store the power on value of the I O pins MPIO2_0 MPIO2_1 MPIO2_2 MPIO2_3 MPIO2_4 MPI...

Page 143: ...own is active a value of 0 indicates the pull down is inactive Register 0xFF20 Multipurpose I O Bank 3 Output MPO3 Read Write R Reserved 7 4 MPO3_ 3 0 Multipurpose I O Bank 3 Output 3 0 The values sto...

Page 144: ...l 100 A pull down resistors which can be disabled with the Multipurpose I O Bank 3 Pull down Enable MPPE3 register 0xFF25 When the SPEN bit 0xFF05 bit 1 is set the MPIO3_2 pin is mapped to the TXD ser...

Page 145: ...pose I O Bank 3 Latch Mask MPLM3 Read Write R Reserved 7 4 MPLM3_ 3 0 Multipurpose I O Bank 3 Latch Mask 3 0 These read write register bits define the write mask for the Multipurpose I O Bank 3 Latch...

Page 146: ...T input signal or the internal power on reset Register 0xFF25 Multipurpose I O Bank 3 Pull down Enable MPPE3 Read Write R Reserved 7 4 MPPE3_ 3 0 Multipurpose I O Bank 3 Pull down Enable 3 0 These rea...

Page 147: ...rol each LED according to Table 8 5 The slow blink and fast blink rates are defined in the LED Blink Rate LBR register 0xFF04 All LED pins have 16 mA open drain drivers Turning the LED off MLOx_xA 0 a...

Page 148: ...drivers Turning the LED off MLOx_xA 0 and MLOx_xB 0 effectively 3 states the driver Register 0xFF32 Multipurpose LED Bank 0L Input MLI0L Read Only R Reserved 7 5 3 1 MLL0_ 3 0 Multipurpose LED Bank 0L...

Page 149: ...ister 0xFF34 Multipurpose LED Bank 0L Latch Mask MLLM0L Read Write R Reserved 7 5 3 1 MLLM0_ 3 0 Multipurpose LED Bank 0L Latch Mask 6 4 2 0 The bits in this read write register define the write mask...

Page 150: ...rresponding bit in MLL0L and MLL0H to be modified Register 0xFF36 Multipurpose LED Bank 0L Latch MLL0L Read Write R Reserved 7 5 3 1 MLL0_ 3 0 Multipurpose LED Bank 0L Latch 6 4 2 0 The bits in this r...

Page 151: ...ower on reset Register 0xFF38 Multipurpose LED Bank 1L Output MLO1L Read Write MLO1_ 3A 0A 3B 0B Multipurpose LED Bank 1L Output 7 0 These bits control the Multipurpose LED Bank 1 pins MPLED1_0 MPLED1...

Page 152: ...to Table 8 6 The slow blink and fast blink rates are defined in the LED Blink Rate LBR register 0xFF04 All LED pins have 16 mA open drain drivers Turning the LED off MLOx_xA 0 and MLOx_xB 0 effective...

Page 153: ...xFF39 they can be used as input pins Register 0xFF3C Multipurpose LED Bank 1L Latch Mask MLLM1L Read Write R Reserved 7 5 3 1 MLLM1_ 3 0 Multipurpose LED Bank 1L Latch Mask 6 4 2 0 These read write re...

Page 154: ...ding bit in MLL1L and MLL1H to be modified Register 0xFF3E Multipurpose LED Bank 1L Latch MLL1L Read Write R Reserved 7 5 3 1 MLL1_ 3 0 Multipurpose LED Bank 1L Latch Mask 6 4 2 0 The bits in these re...

Page 155: ...rnal power on reset Register 0xFF40 Multipurpose LED Bank 2L Output MLO2L Read Write MLO2_ 3A 0A 3B 0B Multipurpose LED Bank 2L Output 7 0 These bits control the Multipurpose LED Bank 2 pins MPLED2_0...

Page 156: ...Table 8 7 The slow blink and fast blink rates are defined in the LED Blink Rate LBR register 0xFF04 All LED pins have 16 mA open drain drivers Turning the LED off MLOx_xA 0 and MLOx_xB 0 effectively 3...

Page 157: ...8 0xFF39 they can be used as input pins Register 0xFF44 Multipurpose LED Bank 2L Latch Mask MLLM2L Read Write R Reserved 7 5 3 1 MLLM2_ 3 0 Multipurpose LED Bank 2L Latch Mask 6 4 2 0 The bits in this...

Page 158: ...corresponding bit in MLL2L and MLL2H to be modified Register 0xFF46 Multipurpose LED Bank 2L Latch MLL2L Read Write R Reserved 7 5 3 1 MLL2_ 3 0 Multipurpose LED Bank 2L Latch 6 4 2 0 These read writ...

Page 159: ...h 6 4 2 0 These read write register bits store the power on value of the I O pins MPLED2_4 MPLED2_6 and MPLED2_7 The values on these pins are latched into this register on the deasserting edge of the...

Page 160: ...8 34 System Registers...

Page 161: ...current published standards and are only discussed briefly in this technical manual Please refer to the appropriate standards documentation for the latest information Section 9 1 Operating Requiremen...

Page 162: ...rage temperature 55 150 C Vdd Supply voltage 0 5 5 0 V Vin Input voltage Vss 0 3 VDD 0 3 V Ilp 2 2 2 V Vpin 8 V Latch up current 150 mA ESD3 3 SCSI pins only Electrostatic discharge 2 K V Mil STD 883C...

Page 163: ...IO SIO SCD SCD SATN SATN SBSY SBSY SSEL SSEL SRST SRST Symbol Parameter Min Max Units Test Conditions IO Source current 7 13 mA Asserted state IO Sink current 7 13 mA Asserted state IO Source current...

Page 164: ...oltage asserting 60 mV VI LVD receiver voltage negating 60 mV VI 2 VCM VCM 0 7 1 8 V VI 2 Table 9 5 SE SCSI and SFF 8067 Signals SD 7 0 SD 7 0 SHID 2 0 SHID 2 0 SDP0 SDP0 SREQ SREQ SACK SACK Symbol Pa...

Page 165: ...ional 80C32 Signals AD 7 0 A 15 8 ALE PSEN RD WR Symbol Parameter Min Max Units Test Conditions Vih Input high voltage 2 0 5 0 V Vil Input low voltage Vss 0 5 0 8 V Voh Output high voltage 2 4 Vdd V 4...

Page 166: ...gnals MPIO0 7 0 MPIO1 7 0 MPIO2 7 0 MPIO3 3 0 Symbol Parameter Min Max Units Test Conditions Vih Input high voltage 2 0 5 0 V Vil Input low voltage Vss 0 5 0 8 V Voh Output high voltage 2 4 Vdd V 4 mA...

Page 167: ...ming Figure 9 3 SYM53C040 Clock Waveforms CLK SCLK t3 t4 t1 t2 Table 9 12 SYM53C040 Clock Timings1 1 Duty cycle not to exceed 60 40 Symbol Parameter Min Max Units t1 CLK clock period 25 DC ns t2 CLK l...

Page 168: ...2 Reset Signal Figure 9 4 Reset Waveforms CLK RESET t1 t2 Table 9 13 Reset Timings Symbol Parameter Min Max Units t1 Reset Input Pulse Width 10 tclk ns t1 Reset Output Pulse Width 15 tclk ns t2 Reset...

Page 169: ...Symbol Parameter Min Max Units T1 ALE pulse width duration of positive ALE pulse 23 ns T2 PSEN pulse width duration of negative PSEN pulse 75 ns T3 PSEN falling to instruction valid maximum delay fro...

Page 170: ...lse width Minimum time RD is low 50 ns t10 RD to valid data in Maximum delay from RD falling to data valid 48 ns t11 Data hold after RD 0 ns t12 Data float after RD 5 ns t6 Address Valid to ALE Fallin...

Page 171: ...se width Minimum time WR is low 50 ns t15 Data setup to WR Minimum time data is valid prior to WR rising 50 ns t16 Data hold after WR Minimum time data is valid after WR rising 20 ns t6 Address Valid...

Page 172: ...pply to register accesses to control the MPIO and MPLED pins Please refer to Chapter 2 for more information on specifying the operation of these pins Table 9 17 Multipurpose I O and LED Timings Parame...

Page 173: ...l Description Min Max Units t1 Hold time after start condition 4 0 s t2 Data hold 0 s t3 Data setup 250 ns t4 SCL low period 4 7 s t5 SCL high period 4 0 s Table 9 19 Two Wire Interface Timings Fast M...

Page 174: ...7 Write Phase Waveforms PESI SEL 3 0 t1 t2 Driven By Drive DSK_WR Driven By Drive DSK_RD Driven By Drive ENCL_ACL Driven By SYM53C040 D 3 0 Driven By SYM53C040 SEL 3 0 PESI t3 Driven By Drive DSK_WR D...

Page 175: ...ter Description Min Max Units t1 PESI LOW to ENCL_ACK LOW 1 s t2 Data hold from PESI LOW 1 s t3 Data setup to DSK_WR LOW 100 ns t4 Data setup to ENCL_ACK LOW 100 ns PESI t4 Driven By Drive DSK_WR Driv...

Page 176: ...d Waveforms Table 9 21 Initiator Asynchronous Send Timings Symbol Description Min Max Units t1 SACK asserted from SREQ deasserted 5 ns t2 SACK deasserted from SREQ deasserted 5 ns t3 Data setup to SAC...

Page 177: ...s Table 9 22 Initiator Asynchronous Receive Timings Symbol Description Min Max Units t1 ACK asserted from REQ deasserted 5 ns t2 ACK deasserted from REQ deasserted 5 ns t3 Data setup to REQ asserted 0...

Page 178: ...forms Table 9 23 Target Asynchronous Send Timings Symbol Description Min Max Units t1 REQ deasserted from REACKQ asserted 5 ns t2 REQ asserted from ACK deasserted 5 ns t3 Data setup to REQ asserted 55...

Page 179: ...s Table 9 24 Target Asynchronous Receive Timings Symbol Description Min Max Units t1 REQ deasserted from ACK asserted 5 ns t2 REQ asserted from ACK deasserted 5 ns t3 Data setup to ACK asserted 0 t4 D...

Page 180: ...for Interconnecting and Packaging Electronic Circuits Specification IPC SM 782 Surface Mount Design and Land Pattern Standard is an established method of designing land patterns Feature size and tole...

Page 181: ...hanical Drawing Sheet 1 of 2 Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing represent...

Page 182: ...Mechanical Drawing Sheet 2 of 2 Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing repres...

Page 183: ...V Mechanical Drawing Important This drawing may not be the latest version For board layout and manufacturing obtain the most recent engineering drawings from your LSI Logic marketing representative by...

Page 184: ...9 24 Electrical Characteristics...

Page 185: ...SCSI Data CSD 0xFC00 Read Only 4 3 Current SCSI Data High CSDHI 0xFC08 Read Only 4 13 Data ES0 ES1 ES2 100 0xFD00 0xFD02 Read Write 6 4 DMA Interrupt DMAI 0xFC14 Read Write 4 17 DMA Send DSR 0xFC05 Wr...

Page 186: ...Multipurpose I O Bank 1 Input MPI1 0xFF12 Read Only 8 12 Multipurpose I O Bank 1 Latch MPL1 0xFF14 Read Write 8 13 Multipurpose I O Bank 1 Latch Mask MPLM1 0xFF13 Read Write 8 13 Multipurpose I O Ban...

Page 187: ...Output MLO0L 0xFF30 Read Write 8 21 Multipurpose LED Bank 1H Input MLI1H 0xFF3B Read Only 8 27 Multipurpose LED Bank 1H Latch MLL1H 0xFF3F Read Write 8 29 Multipurpose LED Bank 1H Latch Mask MLLM1H 0...

Page 188: ...t Parity Interrupt RPI 0xFC07 Read Only 4 12 Select Enable SER 0xFC04 Write Only 4 10 Select Enable High SENHI 0xFC0C Write Only 4 13 Start DMA Initiator Receive SDIR 0xFC07 Write Only 4 12 Start DMA...

Page 189: ...Output Data ODR Write Only 4 3 0xFC01 Initiator Command ICR Read Write 4 4 0xFC02 Mode MR Read Write 4 6 0xFC03 Target Command TC Read Write 4 8 0xFC04 Current SCSI Bus Status CSBS Read Only 4 9 0xFC0...

Page 190: ...MDATA1 Read Write 5 6 0xFD00 0xFD02 Own Address ES0 ES1 ES2 000 Read Write 6 3 0xFD00 0xFD02 Clock ES0 ES1 ES2 010 Read Write 6 3 0xFD00 0xFD02 Data ES0 ES1 ES2 100 Read Write 6 4 0xFD01 0xFD03 Contr...

Page 191: ...BR Read Write 8 6 0xFF05 System Control SYSCTRL Read Write 8 7 0xFF08 Multipurpose I O Bank 0 Output MPO0 Read Write 8 8 0xFF09 Multipurpose I O Bank 0 Enable MPE0 Read Write 8 9 0xFF0A Multipurpose I...

Page 192: ...se I O Bank 3 Latch MPL3 Read Write 8 20 0xFF25 Multipurpose I O Bank 3 Pull down Enable MPPE3 Read Write 8 20 0xFF30 Multipurpose LED Bank 0L Output MLO0L Read Write 8 21 0xFF31 Multipurpose LED Bank...

Page 193: ...e 8 29 0xFF41 Multipurpose LED Bank 2H Output MLO2H Read Write 8 30 0xFF42 Multipurpose LED Bank 2L Input MLI2L Read Only 8 30 0xFF43 Multipurpose LED Bank 2H Input MLI2H Read Only 8 31 0xFF44 Multipu...

Page 194: ...A 10 Register Summary...

Page 195: ...ADB bit 4 5 address space mapping options 2 4 addressed as slave bit 6 8 AIO assert I_O bit 2 8 AIO bit 4 8 AIP bit 4 4 AMSG assert MSG bit 2 8 AMSG bit 4 8 ARB bit 4 7 arbitrate bit 4 7 arbitration...

Page 196: ...ation high register 4 16 DMA source destination low register 4 16 DMA status 2 11 DMA status register 4 14 DMA target transfers 2 6 DMA transfer length 2 11 DMA transfer length register 4 15 DMA trans...

Page 197: ...d hardware interrupts 2 32 register bits used 2 28 SCSI 2 27 2 29 SCSI bus reset 2 30 SFF 8067 2 31 two wire serial 2 31 IOD bit 4 14 IRA bit 4 11 ISR register 7 7 ITF0 control bit 6 11 ITF0 SCL input...

Page 198: ...E2 register 8 17 MPPE3 register 8 20 MSG bit 4 9 multipurpose I O bank 0 enable register 8 9 input register 8 9 latch mask register 8 10 latch register 8 10 output register 8 8 pull down enable regist...

Page 199: ...select 2 23 serial ROM 2 22 serial ROM chip address 2 22 power on reset 2 23 program memory 2 3 programmed I O transfers 2 8 protocol SCSI 2 3 R RD bit 5 6 5 7 RDATA0 RDATA1 register 5 3 read data reg...

Page 200: ...D 4 10 EPC 4 6 EPI 4 6 ERO 8 7 ES 1 2 6 5 6 7 ES0 6 5 6 6 EXS0_INT 7 8 EXS1_INT 7 8 external interrupt enable 6 5 6 7 8 8 fast blink rate 8 7 FBR 1 0 8 7 FIBD 1 0 8 4 first instruction branch destinat...

Page 201: ...1 enable 8 12 input 8 12 latch 8 13 latch mask 8 13 output 8 11 pull down enable 8 14 multipurpose I O bank 2 enable 8 15 input 8 15 latch 8 16 latch mask 8 16 output 8 14 pull down enable 8 17 multi...

Page 202: ...6 6 6 7 STO 6 6 6 7 stop 6 6 6 7 STS 6 8 T1CLR 7 9 T1EXP 7 8 T1FC 7 0 7 10 T1IEN 7 9 T1PS 7 9 T1RUN 7 8 T1SC 6 0 7 10 T1TH 7 0 7 9 T2CLR 7 11 T2EXP 7 11 T2FC 7 0 7 13 T2IEN 7 11 T2PS 7 11 T2RUN 7 11 T...

Page 203: ...5 6 MCR 7 6 MDATA0 MDATA1 5 6 miscellaneous 6 9 MLI0H 8 23 MLI0L 8 22 MLI1H 8 27 MLI1L 8 26 MLI2H 8 31 MLI2L 8 30 MLL0H 8 25 MLL0L 8 24 MLL1H 8 29 MLL1L 8 28 MLL2H 8 33 MLL2L 8 32 MLLM0H 8 24 MLLM0L...

Page 204: ...5 power on configuration zero 8 4 reset parity interrupt 4 12 select enable 4 10 select enable register high 4 13 start DMA initiator receive 4 12 start DMA target receive 4 12 status register reads...

Page 205: ...13 SENHI register 4 13 serial port enable bit 8 8 serial ROM download chip address mapping 2 22 external ROM 2 22 selecting a two wire serial interface 2 23 SFF 8067 interface 2 4 2 23 2 24 control 2...

Page 206: ...15 transfer length 2 13 TW0_INT bit 7 7 TW1_INT bit 7 7 two wire Interface 0 interrupt bit 7 7 two wire interface 0 interrupt bit 7 14 two wire interface 1 interrupt bit 7 7 7 13 7 15 two wire interfa...

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