LSI Symbios SYM53C040, Technical Manual

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8-7
R Reserved [7:6]
FBR[1:0] Fast Blink Rate [5:4]
These bits define the fast blink rate for the LED output
pins, as shown in
Table 8.3 .
R Reserved [3:2]
SBR[1:0] Slow Blink Rate [1:0]
These bits define the slow blink rate for the LED output
pins, as shown in
Table 8.4 .
Register: 0xFF05
System Control (SYSCTRL)
Read/Write
ERO Enable Reset Output 7
When set, this bit enables the internally generated
watchdog time-out reset to be driven on the external
reset pin. This bit is not affected by a soft reset.
Table 8.3 Fast LED Blink Rates (40 MHz Internal
Clock)
FBR1 FBR0 Fast Blink Rate Fast Blink Period
0 0 8 Hz 0.0625 s on/0.0625 s off
0 1 4 Hz 0.125 s on/0.125 s off
1 0 2 Hz 0.25 s on/0.25 s off
1 1 1 Hz 0.5 s on/0.5 s off
Table 8.4 Slow LED Blink Rates (20 MHz Internal
Clock)
SBR1 SBR0 Slow Blink Rate Slow Blink Period
0 0 2 Hz 0.25 s on/0.25 s off
0 1 1 Hz 0.5 s on/0.5 s off
1 0 0.5 Hz 1 s on/1 s off
1 1 0.25 Hz 2 s on/2 s off
7 6 3 2 1 0
ERO R LVD SPEN EIEN
Defaults:
0 0 0 0 0 0 0 0