LSI LSI53C896, Technical Manual

Page: 39 / 370

PCI Functional Description 2-13
2.1.4.3 Memory Read Caching
Which type of Memory Read command gets issued depends on the
starting location of the transfer and the number of bytes to be transferred.
During reads, no cache alignment is done (this is not required nor
optimal per PCI 2.1 specification) and reads will always be either a
programmed burst length in size, as set in the
DMA Mode (DMODE) and
Chip Test Three (CTEST3) registers. In the case of a transfer which is
smaller than the burst length, all bytes for that transfer will be read in one
PCI burst transaction. If the transfer will cross a Dword boundary
(A[1:0] = 0b00) a Memory Read Line command is issued. When the
transfer will cross a cache boundary (depends on the cache line size
programmed into the PCI configuration register), a Memory Read
Multiple command is issued. If a transfer will not cross a Dword or cache
boundary or if cache mode is not enabled a Memory Read command is
issued.
2.1.4.4 Memory Write Caching
Writes will be aligned in a single burst transfer to get to a cache
boundary. At that point, Memory Write and Invalidate commands will be
issued and will continue at the burst length programmed into the
DMA
Mode (DMODE) register. Memory Write and Invalidate commands are
issued as long as the remaining byte count is greater than the Memory
Write and Invalidate threshold. When the byte count goes below this
threshold, a single Memory Write burst will be issued to complete the
transfer. The general pattern for PCI writes will is:
•
A single Memory Write to align to a cache boundary.
•
Multiple Memory Write and Invalidates.
•
A single data residual Memory Write to complete the transfer.
Table 2.2 describes PCI cache mode alignment.
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