LSI LSI53C896, Technical Manual

Page: 265 / 370

Load/Store Instructions 5-37
5.6.4 Third Dword
Figure 5.14 Memory Move Instructions - Third Dword
TEMP Register [31:0]
These bits contain the destination address for the
Memory Move.
If the destination address is in the 64-bit address space,
the bits will be contained in the
Memory Move Write
Selector (MMWS) register.
5.7 Load/Store Instructions
The Load/Store instructions provide a more efficient way to move data
from/to memory to/from an internal register in the chip without using the
normal memory move instruction.
The load/store instructions are represented by two-Dword opcodes. The
first Dword contains the
DMA Command (DCMD) and DMA Byte Counter
(DBC) register values. The second Dword contains the DMA SCRIPTS
Pointer Save (DSPS) value. This is either the actual memory location of
where to load/store, or the offset from the Data Structure Address (DSA) ,
depending on the value of bit 28 (DSA Relative).
For load operations where the data is read from the 64-bit address
space, the upper Dword of address resides in the
Memory Move Read
Selector (MMRS) register. For store operations where the data is written
to the 64-bit address space, the upper Dword of address resides in the
Memory Move Write Selector (MMWS) register.
31 0
TEMP Register
31 0
MMWS Register
*