LSI LSI53C896, Technical Manual

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4-102 Registers
This bit also enables the flushing mechanism to flush
data during a data in phase mismatch in a more efficient
manner.
PMJCTL Jump Control 6
This bit controls which decision mechanism is used when
jumping on phase mismatch. When this bit is cleared the
LSI53C896 will use jump address one
Phase Mismatch
Jump Address 1 (PMJAD1) when the WSR bit is cleared
and jump address two Phase Mismatch Jump Address 2
(PMJAD2) when the WSR bit is set. When this bit is set
the LSI53C896 will use jump address one (PMJAD1) on
data out (data out, command, message out) transfers and
jump address two (PMJAD2) on data in (data in, status,
message in) transfers. Note that the phase referred to
here is the phase encoded in the block move SCRIPTS
instruction, not the phase on the SCSI bus that caused
the phase mismatch.
ENNDJ Enable Jump On Nondata Phase Mismatches 5
This bit controls whether or not a jump is taken during a
nondata phase mismatch (i.e. message in, message out,
status, or command). When this bit is cleared, jumps will
only be taken on Data-In or Data-Out phases and a
phase mismatch interrupt will be generated for all other
phases. When this bit is set, jumps will be taken
regardless of the phase in the block move. Note that the
phase referred to here is the phase encoded in the block
move SCRIPTS instruction, not the phase on the SCSI
bus that caused the phase mismatch.
DISFC Disable Auto FIFO Clear 4
This bit controls whether or not the FIFO is automatically
cleared during a Data-Out phase mismatch. When set,
data in the DMA FIFO as well as data in the
SCSI Output
Data Latch (SODL) and SODR (a hidden buffer register
which is not accessible) registers will not be cleared after
calculations on them are complete. When cleared, the
DMA FIFO, SODL and SODR will automatically be
cleared. This bit also disables the enhanced flushing
mechanism.
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