LSI LSI53C1000, Technical Manual

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5-12 SCSI SCRIPTS Instruction Set
If the SCSI phase bits do not match the value stored in
the
SCSI Status One (SSTAT1) register, the LSI53C1000
generates a phase mismatch interrupt and the instruction
is not executed.
During a Message-Out phase, after the LSI53C1000 has
performed a select with Attention (or SATN/ is manually
asserted with a Set ATN instruction), the LSI53C1000
deasserts SATN/ during the final SREQ/SACK/
handshake.
When the LSI53C1000 is performing a block move for
Message-In phase, it does not deassert the SACK/ signal
for the last SREQ/SACK/ handshake. Clear the SACK/
signal using the Clear SACK I/O instruction.
SCSIP[2:0] SCSI Phase [26:24]
This field defines the desired SCSI information transfer
phase. When the LSI53C1000 operates in the initiator
mode, these bits are compared with the latched SCSI
phase bits in the
SCSI Status One (SSTAT1) register.
When the LSI53C1000 operates in the target mode, it
asserts the phase defined in this field. The following table
describes the possible combinations and the
corresponding SCSI phase.
TC[23:0] Transfer Counter [23:0]
This 24-bit field specifies the number of data bytes to be
moved between the LSI53C1000 and system memory.
The field is stored in the
DMA Byte Counter (DBC)
register. When the LSI53C1000 transfers data to/from
memory, the DBC register is decremented by the number
of bytes transferred. In addition, the
DMA Next Address
MSG C_D I_O SCSI Phase
0 0 0 ST Data-Out
0 0 1 ST Data-In
0 1 0 Command
0 1 1 Status
1 0 0 DT Data-Out
1 0 1 DT Data-In
1 1 0 Message-Out
1 1 1 Message-In