LSI LSI53C1000, Technical Manual

Page: 228 / 384

4-118 Registers
If CRCDSEL = 0b11, this register contains the saved bad
CRC value that was calculated when a CRC error was
detected. After a CRC error is detected, this register is
not overwritten until the error condition is cleared.
Registers: 0xE8–0xEF
Reserved
This register is reserved.
Registers: 0xF0–0xF1
DMA FIFO Byte Count (DFBC)
Read Only
DFBC DMA FIFO Byte Count [15:0]
This 16-bit read only register contains the actual number
of bytes contained in the DMA FIFO. This register is not
stable while data is actually being transferred. This
register can be used during error recovery.
Registers: 0xF2–0xF3
Reserved
This register is reserved.
31 0
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
15 0
DFBC
x x x x x x x x x x x x x x x x
15 0
R
0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0