Benefits of SureLINK (Ultra160 SCSI Domain Validation)
1-5
AIP is also supported by the LSI53C1000, protecting all nondata phases,
including command, status, and messages. CRC, along with AIP,
provides end-to-end protection of the SCSI I/O.
SureLINK Domain Validation provides 3 levels of integrity checking:
Basic (level 1), Enhanced (level 2), and Margined (level 3). Further
information on SureLINK is available in
SureLINK (Ultra160 SCSI Domain Validation).”
An advantage of Ultra160 SCSI is that it significantly improves SCSI
bandwidth while preserving existing hardware and software investments.
The primary software changes required are to enable the chip to perform
synchronous negotiations for Ultra160 SCSI rates and to enable the
clock quadrupler. Ultra160 SCSI uses the same connectors as Ultra
SCSI and Ultra2 SCSI.
contains more information on migrating
an Ultra SCSI or Ultra2 SCSI design to an Ultra160 SCSI design.
1.3 Benefits of SureLINK (Ultra160 SCSI Domain Validation)
SureLINK represents the very latest SCSI interconnect management
solution. It ensures robust and low risk Ultra160 SCSI implementations
by extending the Domain Validation guidelines documented in the ANSI
T10 SPI-3 specifications. Domain Validation verifies that the system is
capable of transferring data at Ultra160 speeds, allowing it to renegotiate
to lower speed and bus width if necessary. SureLINK is the software
control for the manageability enhancements in the LSI53C1000. Fully
integrated in the Storage Device Management System (SDMS™)
software solution, SureLINK provides Domain Validation at boot time as
well as throughout system operation. SureLINK extends to the DMI
(Desktop Management Interface) based System Management
components of SDMS, providing the network administrator remote
management capability.
SureLINK Domain Validation provides 3 levels of integrity checking:
Basic (level 1), Enhanced (level 2), and Margined (level 3). The basic
check consists of an inquiry command to detect gross problems. The
enhanced check sends a known data pattern using the Read and Write
Buffer commands to detect additional problems. Margined check verifies
that the physical parameters have some degree of margin. By varying
LVD drive strength and REQ/ACK timing characteristics, level 3 verifies
Summary of Contents for LSI53C1000
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Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
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Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...