4-8
Registers
Register: 0x0D
Latency Timer (LT)
Read/Write
LT
Latency Timer
[7:0]
The Latency Timer register specifies, in units of PCI bus
clocks, the value of the Latency Timer for this PCI bus
master. The LSI53C1000 supports this timer. All eight
bits are writable, allowing latency values of 0–255 PCI
clocks. Use the following equation to calculate an
optimum latency value for the SCSI function.
Latency = 2 + (Burst Size * (typical wait 1))
Values greater than optimum are also acceptable.
Register: 0x0E
Header Type (HT)
Read Only
HT
Header Type
[7:0]
This 8-bit register identifies the layout of bytes 0x10
through 0x3F in configuration space and also whether or
not the device contains multiple functions. Since the
LSI53C1000 is not a multifunction controller, the value of
this register is 0x00.
7
0
LT
0
0
0
0
0
0
0
0
7
0
HT
0
0
0
0
0
0
0
0
Summary of Contents for LSI53C1000
Page 6: ...vi Preface...
Page 16: ...xvi Contents...
Page 28: ...1 12 Introduction...
Page 234: ...4 124 Registers...
Page 314: ...6 40 Specifications This page intentionally left blank...
Page 318: ...6 44 Specifications This page intentionally left blank...
Page 344: ...6 70 Specifications This page intentionally left blank...
Page 350: ...6 76 Specifications Figure 6 42 LSI53C1000 329 Ball Grid Array Bottom view...
Page 352: ...6 78 Specifications...
Page 360: ...A 8 Register Summary...
Page 376: ...IX 12 Index...