LSI L64777, Technical Manual

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Input Synchronization 2-13
bitstream. If the microprocessor interface selects internal
synchronization, the L64777 looks for an 8-bit sync pattern S, repeated
in the DIN[0] input data stream with a given period of P bytes. For an
MPEG-2 DVB transmission, S = 0x47 and P = 204. The values S and P
are programmable in the chip to accommodate all applications based on
MPEG and MPEG-derived standards.
Parallel operation requires byte-aligning the SYNC_BYTE to achieve
data-dependant synchronization. For serial input, the L64777 searches
the SYNC_BYTE in all possible bit positions and automatically detects
the byte-alignment.
In the L64777, the sync algorithm is fixed to a procedure with
programmable values of S and P. In order to achieve the required
functionality at the lowest possible gate count, you can select from three
values of track steps, which are the number of flywheel repetitions
required to declare the states SYNCOK and loss-of-sync. There are two
phases to the sync algorithm procedure: the sync acquisition phase, and
the sync tracking phase.
2.4.1 Sync Acquisition Phase
In the sync acquisition phase, the number of sync detections required for
sync and loss is programmable from 3 to 5. TS is the designation for the
number of track steps. After TS error-free consecutive detections of the
sync byte S at the correct locations, the L64777 declares synchroniza-
tion; if a mismatch occurs, it goes back to the search state.
Validating the detection of the sync word three times ensures a
probability of false alarm equal to P
fa
= (2
−
8
)
3
= 6*10
−
8
. Validating the
detection of the sync word five times insures a probability of false alarm
equal to P
fa
= (2
−
8
)
5
= 9*10
−
13
.
Figure 2.7 shows the states occurring in the sync acquisition phase.
Figure 2.7 Sync Acquisition Phase
S0
b0
S1
a0
S2
a a
To State S3
b