LSI L64777, Technical Manual

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B-2 PLL Divider Settings and L64724/34 Connection
The QAM modulator is programmed for its configuration and operational
modes through the Serial Microprocessor interface. The L64777
synchronizes with the input data, derives the operating clock (based on
the operational mode), carries out clock conversion with appropriate
FIFO management, inserts the sync and error flags, and performs
scrambling, RS encoding, and convolutional interleaving.
Signal frequencies at the symbol clock (SCLK) and operating clock
(OCLK) outputs of the L64777 indicate appropriate locking of the internal
timing system with respect to the incoming data rates when the input is
from an MPEG source or the L64724 satellite receiver. The relationship
among the SCLK, OCLK, and input data rate is described in the following
subsections. If the same serial host controls both the L64724 and the
L64777, hold the L64777 in reset until the L64724 PLL has been
programmed.
B.2 PLL Driver Settings for Typical Applications
Table B.1 lists the L64777’s PLL driver settings for Mode 1.
Note that the above settings assume a block length of 204 bytes with 16
invalid bytes and TS is the effective input rate attained, considering the
number of cycles with valid data.
Table B.1 Typical Settings of CNT_I and CNT_O
ICLK
in MHz
QAM
mode
TS rate
in Mbyte/s
/Mbit/s
CNT_I
(decimal)
CNT_O
(decimal)
Frequency at
Phase
Comparator
in MHz
OCLK
in MHz
7.32 256 6.75/54.0 8 32 0.92 29.30
5.17 64 4.76/38.1 6 32 0.87 27.56
4.33 32 3.99/31.9 5 32 0.87 27.69
3.42 16 3.15/25.2 4 32 0.86 27.34