4/29/2020
Loongson 3A3000 / 3B3000 Processor User Manual
68
80
31: 0
Interrupt_mask
[127: 96]
32
0x0
R / W
HT bus interrupt enable register [127: 96],
Corresponding to interrupt line 1 / HT HI Corresponding to interrupt line 5
Offset:
0xb0
Reset value:
0x00000000
name:
HT bus interrupt enable register [159: 128]
Table 10-38 Definition of HT Bus Interrupt Enable Register (5)
Bit field
Bit field name
Bit width reset value Visit description
31: 0
Interrupt_mask
[159: 128]
32
0x0
R / W
HT bus interrupt enable register [159: 128],
Corresponding to interrupt line 2 / HT HI Corresponding to interrupt line 6
Offset:
0xb4
Reset value:
0x00000000
name:
HT bus interrupt enable register [191: 160]
Table 10-39 Definition of HT Bus Interrupt Enable Register (6)
Bit field
Bit field name
Bit width reset value Visit description
31: 0
Interrupt_mask
[191: 160]
32
0x0
R / W
HT bus interrupt enable register [191: 160],
Corresponding to interrupt line 2 / HT HI Corresponding to interrupt line 6
Offset:
0xb8
Reset value:
0x00000000
name:
HT bus interrupt enable register [223: 192]
Table 10- 40 HT bus interrupt enable register definition (7)
Bit field
Bit field name
Bit width reset value Visit description
31: 0
Interrupt_mask
[223: 192]
32
0x0
R / W
HT bus interrupt enable register [223: 192],
Corresponding to interrupt line 3 / HT HI Corresponding to interrupt line 7
Offset:
0xbc
Reset value:
0x00000000
name:
HT bus interrupt enable register [255: 224]
Table 10- 41 HT Bus Interrupt Enable Register Definition (8)
Bit field
Bit field name
Bit width reset value Visit description
31: 0
Interrupt_mask
[255: 224]
32
0x0
R / W
HT bus interrupt enable register [255: 224],
Corresponding to interrupt line 3 / HT HI Corresponding to interrupt line 7
Page 85
Godson 3A3000 / 3B3000 Processor User Manual • Volume 1
10.5.10
Interrupt Discovery & Configuration
Offset:
0xc0
Reset value:
0x80000008
name:
Interrupt Capability
Table 10- 42 Inte upt Capab l ty Register Definition
Bit field
Bit field name
Bit width reset value Visit description
31:24
Capabilities Pointer 8
0x80
R
Interrupt discovery and configuration block
23:16
Index
8
0x0
R / W Read register offset address
15: 8
Capabilities Pointer 8
0x0
R
Capabilities Pointer
7: 0
Capability ID
8
0x08
R
Hypertransport Capablity ID