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Summary of Contents for LNW-80

Page 1: ...LNW80 Technical Reference Manual Pi 5000 5200 882...

Page 2: ...ction or use without express permission is prohibited While every effort was taken in the preparation of this book the publisher assumes no liability for errors or omissions Neither is any liability a...

Page 3: ...AGE B a l 9999999990 I 9099 09098 9999 99999 9O90999999 8668 88889 99989999993 9999999999 3 o ooa a J 8 9 9 9 9 9 9 9 9 9 9 9 9 9 90999 9 9 998 9 9 6 9 9 8 89899 9 80898 8 9 9 9 9 9 9 9 T REG e e o e...

Page 4: ...RFACE 53 POWER SUPPLY 5 3 32K MEMORY EXPANSION 53 FLOPPY DISK CONTROLLER 54 RS232 SERIAL PORT 54 SERIAL CIRCUIT TERMINAL PROGRAM 55 SERIAL PRINTER DRIVER PROGRAM 55 VII 5 8 DOUBLER ALIGNMENT 57 VIII D...

Page 5: ...on can understand the complex internal operation of the LNW80 COMPUTER Remember that any work you do to your LNW80 voids all warranties implied or expressed Also we will not repair or correct owner mo...

Page 6: ...udes not only the Z80A but also the data and address buffers wait logic and system control logic CPU CONTROL CPU CLOCK SYSTEM CONTROL ADDRESS BUS DATA BUS READ ONLY MEMORY ROM The ROM contains non era...

Page 7: ...ARD DATA OUT 8 ADDRESS BUS VIDEO RAM AND PROCESSING The video is used to inform the user what the system is doing All data that is stored in the video ram is automatically displayed on the CRT by the...

Page 8: ...data to parallel form to be received by the CPU This section is used to connect to such devices as modems and serial printers DATA BUS RX BAUD TX BAUD r ENABLE CONTROL SIGNALS RS232C PORT TRANSMIT _...

Page 9: ...e generated through U31 to the CPU pin 24 allowing for the relatively slow access time of the ROM During automatic switching SW1 1 when the floppy address 37EC is decoded along with a logic 0 at IMREQ...

Page 10: ...ay results in proper data setup time to U31 U61 3 is WAITHLD This will increase the wait from the usual one wait state for the Level II ROM s to multiple wait states when reading from the video memory...

Page 11: ...a valid I O address for an I O read or write operation It is used as the enable at U35 15 When combined with a WR IOUT will be enabled U35 9 When ZIORQ is combined with a RD UN will be enabled U35 11...

Page 12: ...FFFF 32K RAM EXPANSION BOARD ROM The LNW80 ROM consists of six EPROMs ROMA is memory mapped from to 2K ROMAl from 2K to 4K ROMB from 4k to 6K R0MB1 from 6K to 8K ROMC from 8K to 10K and ROMC1 from 10...

Page 13: ...er 0 4K 4 8K or 8 12K is enabled PROGRAM RAM The LNW80 utilizes the 16Kxl dynamic memories 4116 type with maximum access time of 200ns The 14 address lines are multiplexed into the 7 address inputs Th...

Page 14: ...oard is designed specifically for the LNW80 computer providing a 62 keypad an 11 key numeric keypad and all the special functions that are available to you through the LNW80 computer an Note that lowe...

Page 15: ...xecutes a divide by 2 This results in 2 input frequencies to the divider chain at U122 In the standard 64 character mode 32CHAR U122 1 will be high so that the B inputs to U122 will be selected theref...

Page 16: ...T6INH U155 9 prevents the completion of its period by clearing U160 and U161 at the end of each horizontal line The frequency of HORTP is 15 750KHz resulting in a period of 63 49us for each line Each...

Page 17: ...creen consists of 22 lines only 16 are displayed and each line has 12 rows LINEl the least signicicant bit of the line counter changes state every 2nd line and thus has the same period as 24 rows or 2...

Page 18: ...O D 00 CD IP CO fO s i 1 CD CD X 5 X CD M W ro II ii CO W i GO B ro M X O V 2 o ro CO B M o 2 CO M o s CD X CD ii H CD ID X CD ro r s o 5 o t 3 W H1 en CD CO O CO H H W O W 2 o CO O VIDEO MEMORY MAP...

Page 19: ...n or CPU address For the following discussion refer to figure 5 the VIDEO MEMORY MAP Note that the low resolution video is defined only within the inner region and that A10 A13 which specify the row c...

Page 20: ...by the video divider chain The selects at U139 U140 U144 and U145 will be high selecting the B inputs U142 specifies whether we are in the inner or extension region Prior to the 64th character HORTP U...

Page 21: ...d At the beginning of the HIRES video read When any of the four inputs goes lo output pin6 will go high clocking U153 DATALAT U153 will be high and U153 6 will be low CLKADRSDTA U137 will go high latc...

Page 22: ...O port 254 bit D3 selects which devices are enabled With D3 l the graphics memory is enabled Note that since the Roms are also disabled by D3 l using the OUT command in basic to turn on this bit will...

Page 23: ...n WRT4116 UI39 4 is inverted through U118 to disable the LORES Ram Figure 6 illustrates the timing diagram during a write operation The read operation is very similar except that GRAMWRT remains high...

Page 24: ...ormation to the 2nd character line GRAPHICS GENERATOR U83 functions as the Graphi The Graphics Character may use the position a 6x12 dot matrix This six rectangles as shown in figure 7 multiplexer It...

Page 25: ...ecause the sixth bit is tied to gnd to blank the sixth dot between characters The inputs to U85 pins 1 2 and 13 represent the restrictions to the LORES graphics shift register If any of its inputs go...

Page 26: ...l and vertical synchronization The VERTICAL TIMING PULSE VERTTP from the divider chain is buffered by U20 8 a CMOS exclusive or acting as a buffer only and drives potentiometer R145 When R145 is set f...

Page 27: ...sign very thin pulses time the voltage level extends f 1 is commonly re tage that would s the white leve y When a pixel above 1 2 volts If most of the al with an oscil extending to 1 2 staying below 4...

Page 28: ...responds to 262 scanned lines including sync The LNW80 refreshes the screen at a rate of 60 hz with 262 lines Countries which have AC power frequencies of 50hz use PAL SECAM or other color systems wit...

Page 29: ...ia two gates of U52 U52 13 COLOR is high U52 2 HRES is high and U52 1 is VIDEO thus the output of U52 12 which allows UI29 to be selected to drive color information to U130 NTSC ROM will go low along...

Page 30: ...7 SYNC and BURST timing into a 3 bit color code the proper R Y COLORB B Y COLORA and LUMINANCE LUM that the MC1372 requires to do the color encoding The NTSC ROM U130 is a high speed bipolar open col...

Page 31: ...33 with timing resistor R107 and no timing capacitor forms a 50 70 nanosecond pulse generator U133 5 drives open collector inverter U162 11 Inverted and pulled up by R97 this generates COLORSYNC COLOR...

Page 32: ...ocks T3 is high BLACK AND WHITE DISPLAY THROUGH THE NTSC CHANNEL In the low or high resolution black and white display modes COLOR is low U68 12 This disables both U131 and U129 Thus U130 receives no...

Page 33: ...tion is accomplished through U21 A B and C Refer to the figure below CASSETTE WAVEFORMS Cassette Input J s JV jv Gate of Q18 A A JV JV 8V max U21 pin 7 J 11 The s R24 and R25 which will el an automati...

Page 34: ...ected through diodes to a summing point at thte anode of Q12 If any of these voltages exceeds approximately 6 2V then CR24 will begin to conduct While the gate of Q12 remains unchanged the anode volta...

Page 35: ...functions of the LNW80 Computer are performed on the expansion board These functions include additional memory real time clock floppy disk controller parallel printer and RS232C serial port The expans...

Page 36: ...2 D2 33 WAIT 34 A3 35 A5 36 A7 37 GND 38 A6 39 GND 40 A2 ROW ADDRESS STROBE SYSTEM RESET COLUMN ADDRESS STROBE ADDRESS INPUT ADDRESS INPUT ADDRESS INPUT ADDRESS INPUT GROUND ADDRESS INPUT ADDRESS INPU...

Page 37: ...ll go low This signal is used to gate RD through U29 pins 9 and 10 respectively U29 8 is then fed into U34 and U35 and is used to enable memory data onto the data bus U34 and U35 is tied to gnd thus e...

Page 38: ...t port This I O port is accessed by either writing or reading from address 37E8 Hex This address is decoded at U30 U31 and U19 When reading the memory address 37E8 the printer status is read through U...

Page 39: ...rovides a divide by 2 resulting in a 2 MHz clock at U9 12 which is then input to U22 3 which again divides by 2 resulting in the 1 MHz clock input to the FLOPPY CONTROLLER U14 U24 effectively produces...

Page 40: ...ting data to and from the disk has the following internal features 1 Cyclic redundancy check and generation for error checking 2 Internally seperates disk head outpput into data 3 Checks for desired s...

Page 41: ...n of the expansion board Drive Selection through Data Lines D0 D3 is clocked into U13 by 37E0 WRITE U19 9 This also triggers the one shot U7A generating the motor on signal The drive selection is only...

Page 42: ...DIAGRAM FIGURE TRl602B UART HANDSHAKE LATCH EIARS 232 and 20mA LEVEL SHIFTERS and DRIVERS EIA LEVEL SHIFTERS TTL EIA J2 DB25 RS 232 C CONNECTOR TD RD TX TX RX J RX MODEM STATUS BUFFER CONFIG SENSE JU...

Page 43: ...mit data and the other with control information word length parity stop bits Refer to the Data Sheet of the Western Digital TR1602B for further details of operation EIA RS232C and 20mA LEVEL SHIFTERS...

Page 44: ...IC The port address decoding IN OUT E8 E9 EA EB is accomplished by U41 and U16 U41 decodes the upper 6 bits E8 and outputs to the strobe inputs of U16 The lower two address bits A1 A0 feed to the A an...

Page 45: ...ts 0 lbit Framing Err l True Ring Indctor Pin 22 DB 25 D3 k Parity Inhibit 1 disabled par Parity Inhibit 1 disabled par Parity Error l True D2 Break Disable Transmit Data Dl Request to Send Pin 4 DB 2...

Page 46: ...37E0RD at U19 7 37E0RD presets U21B clocks a logic 0 into U2IA and enables the output of U3B If bit D7 is a logic 1 then the RTC generated the interupt request The programming of the Real Time Clock c...

Page 47: ...eate an 8 input nor gate whose common output is inverted through U7 and again through U12 U12 8 is used to clock DAL0 into U16 12 Double density operation is selected when DOUBLE and DOUBLE are high a...

Page 48: ...ow and high respectively enabling 8 operation 5 25 and 8 operation may also be selected through software switching When memory location 37EE is written to with data bits D7 l and D6 l the LNDOUBLER wi...

Page 49: ...74LS629 make up the ANALOG PHASE LOCK LOOP DATA SEPERATION For further details refer to the data sheets supplied in this manual PRECISION WRITE PRECOMPENSATION The WD2143 provides an accurate write pr...

Page 50: ...o read or write 4 The status register is read causing the wait logic to issue a wait to the CPU until a the busy bit in the status register goes false b DRQ on the FDC goes true c IRQ on the FDC goes...

Page 51: ...fuses continually blow you may disable the overvoltage protection by removing the SCR s But before doing so disconnect the power supplies Be ready to turn off power if any component begins smoking VID...

Page 52: ...und and pin 7 is A15 Connect pin 8 from the good board to the emitter of the transistor Connect pin 7 from the good board through a 470 ohm resistor to the base of the transistor And connect the colle...

Page 53: ...NEXTX PRINT TEST COMPLETE GOTO10 140 PRINT TEST FAILED PRINT LOC EXPECTED ACTUAL PRINT Y PEEK Y f PEEK X Y Y 1 STOP NEXTX 150 A Y C B A 2047 FOR X A TO B IF PEEK X PEEK Y THEN 130 ELSE 140 151 Y Y Y 1...

Page 54: ...loop on any one location The way the ROM test works is that it peeks the same location on both the good and the bad board and compares Note that if you are using a TRS80 as your good board then some o...

Page 55: ...ng locked on a RD you may trick it by lifting the RD and MREQ lines on the Z80A SCOTCH TAPE TRICK Sometimes the CPU CPU test will not work because connecting to the bad board causes the good board to...

Page 56: ...0 NEXT Z 70 OUT 254 2 80 FOR X 32512 TO 32533 90 READ D 100 POKE X D 110 NEXT X 120 POKE 16526 0 POKE 16527 127 125 LET Y l 130 FOR Z 0 TO 4 140 REM NOW POKE DATA TO BE OUTPUT TO USR ROUTINE 150 POKE...

Page 57: ...ed level should be between 75 and 1 1 volts 10 REM COLOR BAR TEST PROGRAM 20 REM CASSETTE VERSION 30 REM THIS TEST SHOULD GENERATE THE FOLLOWING COLORS 35 REM WHITE GREEN YELLOW RED MAGENTA BLUE BLUE...

Page 58: ...sed in the CPU CPU TEST may be used to trouble shoot the additional 32K of program memory A sample program to test the memory is 10 Y 170 20 FOR X 32767 TO 1 30 POKE X Y 40 A PEEK X 50 IF A Y THEN NEX...

Page 59: ...by the disk drive RS232 HANDSHAKING To test the handshaking short the following points together on J2 J2 4 to J2 5 to J2 6 and J2 8 to J2 20 to J2 22 Load the following progra m 10 FOR Y 0 TO Y 3 OUT...

Page 60: ...ER 40 REM WITH THE LNW RESEARCH SYSTEM EXPANSION CIRCUIT 50 REM BOARD THIS DRIVER PROGRAM IS LEFT IN MEMORY AT A 60 REM LOCATION WHICH IS UNALTERED BY BASIC AND BY USER 70 REM PROGRAMS THE PROGRAM IS...

Page 61: ...eir destination points Problems may also occur at U23 and U39 especially in relation to incorrect data RS232 BAUD RATES On the LNW80 BAUD RATES may only be controlled through hardware switches On the...

Page 62: ...LNDOUBLER 5 8 is a problem AND the LNDOUBLER 5 8 NEEDS ALIGNMENT Equipment Required Digital Voltmeter 1 accuracy lmegohm input impedance Frequency Counter 1 accuracy lKohm input 5MHz Oscilloscope 15M...

Page 63: ...and 2 in the front beneath the keyboard When removing the lid be careful as the LED is connected to the keyboard with wires approximately 8 in length The LED can be removed from the lid by prying the...

Page 64: ...lindrical rods used to support the EI Note that beneath 3 of these rods there are small nylon spacers Remove these also Before you can remove the computer board you must cut the tie wraps holding the...

Page 65: ...s When making etch cuts use a sharp pointed razor knife and be very careful to cut only the etch specified It is advisable to make the appropiate changes in the schematics as you install these ECN s U...

Page 66: ...53 6 to U170 11 2 U170 8 to U170 9 3 U170 12 to U170 1 4 U170 13 to U121 12 ECN 1003 Purpose To reduce ringing on the MUX and CAS lines a install parts 1 Add a 330 ohm resister from U88 1 to GND 2 Add...

Page 67: ...1008 Purpose To eliminate the possibility of heat damage to board due to heat resulting from CR17 a remove the Bridge at CR17 from board b mount Bridge on case using case chassis as heat sink c connec...

Page 68: ...124 from 220 to 10 ohms 5 R94 from a 1K pot to a 2 2K pot 6 R109 from 2K to 1 2K ohms 7 C113 from 220pf to 47pf MICA 8 U119 from 74S04 to 74LS19 9 C84 from 100pf to a 10 738MHz CRYSTAL NOTE 10 14 ARE...

Page 69: ...OOOOOOO U1 solder side SSboooo pin i 3 install the following jumpers from U36 14 to U20 3 from U36 13 to U20 4 b Cut etch between the following points 1 R34 and R46 near J3 2 R35 and R47 near J3 c Ins...

Page 70: ...N U158 4 TO RGB 4 RED U162 5 TO RGB 5 HORIZONTAL SYNC U158 8 TO RGB 6 GROUND 2 USE 30 GAUGE NON STRANDED WIRE U20 5 TO U162 3 U118 8 TO U162 5 U162 4 TO U162 9 U68 12 TO U158 14 U68 11 TO U158 13 U130...

Page 71: ...and 6 Note that this is only necessary with monitors that do not internally pull up the RED GREEN and BLUE lines This is not necessary with the AMDEC COLOR II RGB MONITOR RGB CIRCUIT LOGIC DIAGRAM U2...

Page 72: ...04 Z80A 74LS244 74LS241 74LS373 74LS138 not used 74LS175 75452 not used not used not used not used not used 74LS32 74LS05 74LS241 74LS244 74LS11 74C86 TL084 not used used used used used used not not n...

Page 73: ...4LS10 74LS244 74LS139 74LS08 not used not used not used not used 74LS00 74LS02 74LS244 74LS244 not used 74LS244 74LS32 74LS175 74LS02 not used not used not used not used 74LS138 74LS30 ROM A1 ROM B1 R...

Page 74: ...74S04 U120 74LS123 U121 74S74 U122 74S157 U123 not used U124 74S74 U1 25 74LS373 U126 74LS174 U127 74166 U128 74LS174 U129 74LS257 U130 NTSC COLOR ROM U131 not used U132 not used U133 74123 U134 not u...

Page 75: ...74LS10 10008 U160 74LS161 10024 U161 74S161 10025 U162 7405 10005 U163 not used U164 not used U165 not used U166 not used U167 74LS161 10024 U168 74LS08 10007 U1 69 74LS11 10009 U170 74LS02 10001 U171...

Page 76: ...6 1K 20016 R37 220K 20024 R38 20K 20022 R39 20K 20022 R40 1 8K 20033 R41 4 7K 20036 R42 3K 20035 R43 10 20025 R44 20K 20022 R45 4 7K 20036 R46 10K 20021 R47 4 7K 20036 R48 10K 20021 R49 10K 20021 R50...

Page 77: ...10 20032 R89 270 20027 R90 910 20032 R91 390 20029 R92 1 2K 20017 R93 470 20014 R94 1K POT 21000 R95 470 20014 R96 1K 20016 R97 220 20010 R98 1K POT 21000 R99 1K POT 21000 R100 470 20014 R101 470 2001...

Page 78: ...20016 20010 21001 20016 20005 20016 20013 20002 20016 20026 20016 20001 20008 20005 20016 20016 20036 21003 21004 CAPACT0RS CERAMIC 25V 20 UNLESS OTHERWISE NOTED C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12...

Page 79: ...0 6 8ufd TANTALUM ELECT 15V 32001 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 6 8ufd TANTALUM ELECT 15V 32001 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 6 8ufd T E 15...

Page 80: ...0pf MICA 5 30004 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 1ufd 30010 not used 50pf MICA 5 25V 30002 9 35pf VARIABLE CAP 33000 1ufd 30010 1ufd 30010 1ufd 30010 1ufd...

Page 81: ...CT 25V 32008 150pf 30008 470pf 30008 9 35pf VAR CAP 33000 15000ufd ELECT 15V 32030 not used ILLANEOUS SEMICONDUCTORS 2N3904 11000 2N3906 11001 7805 5V REGUL 11005 7812 12V REGUL 11006 not used MPU131...

Page 82: ...E 40003 20 PIN LOW PROFILE 40004 24 PIN LOW PROFILE 40005 40 PIN LOW PROFILE 40006 40 PIN MACHINE 40500 MISCELLANEOUS L2 56 uH INDUCTOR 37000 CASSETTE JACK 5 COND DIN RT ANGLE PC 42000 J6 2 COND MOLEX...

Page 83: ...ot used R10 not used R11 not used R12 10K 20021 R13 10K 20021 R14 1K 20016 R15 200K 20023 R16 150 20007 R17 150 20007 R18 150 20007 R19 150 20007 R20 4 7K 20036 R21 4 7K 20036 R22 20K 20022 R23 not us...

Page 84: ...sed used used 20005 20005 20005 20005 20005 20005 20005 20005 20026 used used used CAPACITORS all caps are 25VDC 20 otherwise indicated unless C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11 C12 C13 C14 C15 C16 C1...

Page 85: ...MIC C46 1 ufd CERAMIC C47 1 ufd CERAMIC C48 1 ufd CERAMIC C49 1 ufd CERAMIC C50 1 ufd CERAMIC C51 1 ufd CERAMIC C52 1 ufd CERAMIC C53 6 8 ufd TANTALUM C54 1 ufd CERAMIC C55 6 8 ufd TANTALUM C56 1 ufd...

Page 86: ...4S04 74LS155 74LS14 74LS74 74LS74 74LS08 74163 74163 74LS175 not used 74LS367 74S32 74LS139 74LS30 74LS14 74LS367 74LS244 74LS244 74LS244 74LS241 74LS241 74LS244 TR1602 B 74LS30 4116 200ns 4116 200ns...

Page 87: ...used not used not used not used 10056 10056 10039 10039 10039 10039 10039 10039 10039 10039 10055 MISCELLANE0US Y1 U40 U14 4 000 MHZ CRYSTAL 35000 40 PIN DIP IC SOCKET 40006 40 PIN MACHINE SOCKET 4050...

Page 88: ...0K MULTITURN POT 100K MINI PC POT 20034 20036 20036 20016 20021 20036 20030 20007 20016 20016 20040 20036 20036 20036 20040 20003 20021 20036 20021 21001 21006 21005 C1 C2 C3 C4 C5 C6 C7 C8 C9 C10 C11...

Page 89: ...143 10068 74LS123 10018 74LS05 10006 74LS05 10006 74LS00 10000 WD1691 10067 MB8876 FUJ 1791 COM 10060 40 PIN SOCKET 40006 74LS157 10023 74LS04 10004 74LS158 10034 74LS74 10013 74LS629 10069 74LS74 100...

Page 90: ...COAX WIRE RG174 U 24 GAUGE WIRE STRANDED 20 GAUGE WIRE STRANDED WIRE TIES 3 5 SHRINK TUBING 1 4 SHRINK TUBING 3 8 4 40 NUT 4 40 INTERNAL TOOTH WASHER 4 40x3 4 MACHINE SCREW 4 40x1 4 MACHINE SCREW 4 4...

Page 91: ...LOGIC 6 FD179X APPLICATION NOTES 7 WD2143 01 FOUR PHASE CLOCK GENERATOR 8 74LS629 VOLTAGE CONTROLLED OSCILLATOR 9 MCM4116 16K DYNAMIC RANDOM ACCESS MEMORY PROGRAMABLE UNIJUNCTION TRANSISTER QUAD MDTL...

Page 92: ...e MCM2114 series has a maximum power dissipation of S2S mill Low power versions i e MCM21L14 series are available with a maximum power dissipation of less than 370 mW 1024 Words by 4 Bit Organization...

Page 93: ...5 unless othervv se noted RECOMMENDED DC OPERATING CONDITIONS Psramotar Symbol MCM2114 MCM21L14 Unit Mm Worn Max Min Norn Max Input Load Current Ail Input Pms Vj n to 5 5 VI LI 10 10 MA I O Leakage Cu...

Page 94: ...te Cycle Time WC 200 250 300 450 ns W lte Time tyy 120 135 150 200 ns Write Release Time WB ns Output 3 State From Write OTW 60 70 80 100 ns Data to Write Time Overlap DW 120 135 150 200 ns Data Hold...

Page 95: ...ES n nnnnnnnnnnnnnn nnnnn a 3 b s 2 2 8 UUU UUUuUUuuuuuuuuuuU a TR160ZA CERAMIC PACKAGE OUTLINE J 2 Q jiyctoiyiyGiyo o yo o u MWmfM z it i TR16023 HERMETIC PLASTIC CAVITY PACKAGE OUTLINE C S S O Q Q Q...

Page 96: ...g Vcc WHICH BIASES OFF THE CASCODE DEVICE OF THE TTL OUTPUT IN THE HIGH LEVEL OUTPUT STATE IN THE LOW LEVEL OUTPUT STATE THE TTL OUTPUT 06 V1CE SINKS THE CURRENT SUPPLIED BY DEVICE A v o u 3UUB TB rO...

Page 97: ...together since an output disconnect caoabilitv is provided by me Status Flag Disconnect line pin 16 15 Overrun Error OE A high level output voltage Vqh Of this line indicates that the Data REeaived Fl...

Page 98: ...character to be transmitted is loaded into the TRANSMITTER HOLDING REGISTER on these lines with the THRU Strobe If a character of lass than 8 bits has been selected by WLS 1 and WLS2 the character is...

Page 99: ...to each character as shown in Figure 2 The start element is a single logic zero space data bit that is added to the front of each character The stop element is a logic one mark that is added to the en...

Page 100: ...smitted as they become available This is a very valuable feature when transmitting data from manual entry devices such as a keyboard The major disadvantage of asynchronous trans mission is that it req...

Page 101: ...This parameter is important when operating at the maximum baud rate since the receiver must be prepared to detect the u ss ream o g tal CORPORA r i m next start bit transition after the minimum chara...

Page 102: ...he center of every data bit and outputing the characters in a parallel format with the start parity and stop bits removed Three error flags are also provided to indi cate if the parity was in error a...

Page 103: ...ws the THRE out puts of a number of arrays to be tied to the same data bus Figure 7 illustrates the relative timing of the trans mitter signals After power turn on the master reset should be strobed t...

Page 104: ...l H Ui t IT 2 s C Ul j Ul Z H VI a 4 Z 2 u u X X H m O V M X o t a J 2 u ul ec K UJ Ui ui VI u u s s E o IS u o C3 IS hi WESTERN DIGITAL CORPORA 7 i N 3128 RED HILL AVENUE BOX 2180 NEWPORT BEACH CALIF...

Page 105: ...l the next character is trans ferred to the Holding Register A circuit is also pro vided that checks the first stop bit of each character If the stop bit is not a logic one the Framing Error line will...

Page 106: ...WESTERN DIGITAL TR1602 TR1863 E o o o 9 _ o u s c CO w 3 03 WESTERJV U DIGITAL CQRPQf A r i o N 3128 RED HILL AVENUE BOX 2180 NEWPORT BEACH CALIFORNIA 92663 1714 557 3550 TWX 910 595 1133 101...

Page 107: ...perfect input clocks thus giving a receiver margin of 46 875 In Rgure 10 the start bit could have started as much as one complete clock penod before it was detected as indicated by the shaded area of...

Page 108: ...FM data Each data call is defined by clock pulses A pulse recorded between clock pulses identifies the presence of a logic 1 bit the absence of this pulse is interpreted as a logic bit The Address Ma...

Page 109: ...nput as composite data both dock and data present at the FDDATA input or as separated data in which the data is input to the FDDATA pin and the clock is input to the FD Clock pin When writing informat...

Page 110: ...be considered a snecialized microoro cessor with its own instruction repertoire These are listed in the Tables below The Restore Seek and the three Step commands position the Read Write head over the...

Page 111: ...ternal DRQ sig nal while bit 2 indicates lost data due to overrun or underrun conditions The Type 1 or head positioning i nstructions use bit 1 and 2 as a reflection of the IP and TROO inputs respecti...

Page 112: ...s This signal is reset when ser viced by the computer through reading or loading the DR m Read or Write operation resoecttvely Use 10K pull up resistor to 4 5 This open dram output is set at the compl...

Page 113: ...nput when low for a minimum of 10 usee informs the FD1771 when an index mark is encountered on the diskette This input is sampled whenever a Write Command is received A logic low terminated the comman...

Page 114: ...N WINDOW EXTENSION INCORPORATES ENCODING DECODING AND ADDRESS MARK CIRCUITRY FD1792 4 IS SINGLE DENSITY ONLY FD1795 7 HAS A SIDE SELECT OUTPUT 179X 02 FAWHLY CHARACTERISTICS O FEATURES 1791 1793 1795...

Page 115: ...licon Gate MOS technology and is TTL compatible on all inputs and outputs The 1793 is identical to the 1791 except the DAL iines are TRUE for systems that utilize true data busses The 1735 7 has a sid...

Page 116: ...ors 23 HEAD LOAD TIMING HLT When a logic high is found on the HLT input the head is assumed to be engaged 25 READ GATE 1791 3 RG A high level on this output indicates to the data separator circuitry t...

Page 117: ...ons as a WF input If WF 0 any write command will im mediately be terminated When WG 0 Pin 33 func tions as a VFOE output VFOE will go low during a read operation after the head has loaded and settled...

Page 118: ...bits is a function of the type of command previously executed This register can be read onto the DAL but not loaded from the DAL CRC Logic This logic is used to check or to gener ate the 16 bit Cycli...

Page 119: ...n interfacing with the mini floppy the CLK input is set at 1 MHz for both single density and double density When the clock is at 2 MHz the stepping rates of 3 6 10 and 15 ms are obtainable When CLK eq...

Page 120: ...phase lock loops when to acquire syn chronization When reading from the media in FM RG is made true when 2 bytes of zeroes are detected The FD179X must find an address mark within the next 10 bytes o...

Page 121: ...e Track 1 1 1 1 1 0 E IV Force Interrrupt 1 1 1 ii h h lo TYPE II III COMMANDS m Multiple Record flag Bit 4 m 0 Single Record m 1 Multiple Records an Data Address Mark Bit 0 an 0 FB Data Mark a 1 F8 D...

Page 122: ...compared to the Track Register if there is a match and a valid ID CRC the verification is complete an interrupt is generated and the Busy status bit is reset If there is not a match but there is valid...

Page 123: ...pping motor direction is the same as in the previous step command After a delay determined by theriro field a verification takes place if the V flag is on If the u flag is on the Track Register is upd...

Page 124: ...LOST DATA RECORD MOT FOUND STATUS BITS 5 8 INTRO INTRO RESET SUSY J ves f SET r j 3 K 5 TTG 3 I Sector Length Table Sector Length Field hex Number of Bytes in Sector decimal 00 01 02 03 128 256 512 10...

Page 125: ...OMMAND s flag allows direct control over the SSO Line Pin 2C and is set or reset at the beginning of the command dependent upon the value of this flag READ SECTOR Upon receipt of the Read Sector comma...

Page 126: ...s of the ID field are shown below TRACK ADDR SIDE NUMBER SECTOR ADDRESS SECTOR LENGTH CRC 1 CRC 2 1 2 3 4 5 6 Although the CRC characters are transferred to the computer the FD179X checks for validity...

Page 127: ...is is the only command that will enable the immediate interrupt to clear on a subse quent Load Command Register or Read Status Register STATUS DESCRIPTION Upon receipt of any command except the Force...

Page 128: ...is an inverted copv of the IP input SO BUSY When set command is in progress When reset no command is in progress STATUS FOR TYPE II AND III COMMANDS BIT NAME MEANING S7 NOT READY This bit when set ind...

Page 129: ...Disk Controllers to a drive With the use of an external VCO the WD 1691 will generate the RCLK signal for the WD179X while providing an adjustment pulse PUMP to control the VCO frequency VFOE WF de m...

Page 130: ...irectly to the FD179X TG43 pin If Write Precompen sation is required on TRACKS 44 76 10 v vss Ground 11 READ DATA RDD Composite dock and data stream input from the drive 12 READ CLOCK RCLK RCLK signal...

Page 131: ...n this occurs causing the WD2143 01 to start its pulse gen eration 02 is used as the write data pulse on nominal Early Late f 12 is used for early and 3 is used for late The leading edge of 4 resets t...

Page 132: ...95 and 1797 are identical to the 1791 and 1793 except a side select output has been added that is controlled through the command Register The first consideration in Floppy Disk Design is to de termine...

Page 133: ...CK PER DISK PER TRACK PER DISK 5V SINGLE 1 3125 109 375 64jus 2304 80 640 5W DOUBLE 1 6250 218 750 32jzS 4608 161 280 5V4 SINGLE 2 3125 218 750 64 s 2304 161 280 51 4 DOUBLE 2 6250 437 500 32jzs 4608...

Page 134: ...to CPU address lines in which case the 179X will be memory mapped and addressed like RAM They may also be used under Program Control by tying to a port device such as the 8255 6820 etc As a diagnostic...

Page 135: ...do not With the 8 drive Precompensation may be specified from TRACK 43 on or in most cases all TRACKS If the recommended Precompensation is not specified check with the manufacturer for the proper co...

Page 136: ...AW READ phase relationship to RCLK the PROM is addressed and its data output is used as the counter value A 16MHz clock is required for 8 double density while an 8MHz clock can be used for single dens...

Page 137: ...a recovery and Write Precomp Logic is contained within the 1691 allowing low chip count and PLL re liability The 74S124 supplies the free running VCO output The PUMP UP and PUMP DOWN signals from the...

Page 138: ...ing clocks The output pulse widths are controlled by tying an external resistor to the proper contro inputs AM pulse widths may be set to the same width by tying the 0P vV line through an exter nal le...

Page 139: ...The output frea itncv foi each VCO is established by a single external component either a capacitor or a crystal in combination with voltage sensitive inputs used for frequency control anc requency ra...

Page 140: ...r is disabled V s high and Z is low Caution Crosstalk may occur n the dual devices i LS625 LS626 LSc_ and L5629 when both VCO s are operated simultaneously The pulse svnchron cation gafog ec r on ensu...

Page 141: ...13 18 6 n 121 K l6i H 1101 M i14l 191 V in I15i 1131 11 LS626 OSC VCC 1EN 1FC 1CX1 1CX2 2EN 2FC 2CX1 2CX2 14 r 1Y FC cx CX v OSC G 3i S n lEl 2 6 113 r v 2Y o v osc 1 10 n 12 1151 n OSC GND LS629 10S...

Page 142: ...Organization e i 10 Tolerance on All Power Supplies AM Inputs are Fully TTL Compatible o Three State Fully TTL Compatible Output Common I O Capability When Using Early Write Mode e On Chip Latches for...

Page 143: ...utput Logic Voltage t 0UI M2mA VOL 4 I Vac I NOTES i Alt voHaget ri Toreneea to V ss V BB mull be aopi ea Before and removed afte oihe supply voltages 2 Output voltage wiii swing from V ss to V cc und...

Page 144: ...200 ns Column to Row Strobe Precnaroe Time ICRP 20 20 20 20 ns RAS Hold Time RSH 100 135 165 200 ns Pefiesh Period RFSH 2 0 2 0 2 0 20 ms WRITE Command Setup Time wes 20 20 20 20 ns CAS to WRITE Delay...

Page 145: ...READ CYCLE TIMING nS _ J V IHC RAH RSH l CAS Lg I BP e z v Add A WMWy V 5W xwxmww RP CRP m 1 RCH Lo I xW W t r WRITE CYCLE TIMING ADDRESSES Din BC K RCD a O CSH RAH CAH H J Na j t ASC o J f MM V H 140...

Page 146: ...BEAD WRITE READ MODIFY WRITE CYCLE It t RWC PAS KX asc bH k cahbb A S_ k cRP icr v Acldfeis WM CWL RWL J o i AWA AV RAS ONLY REFRESH TIMING Note CAS V hc WRITE Don t Co 1 f RAW ADDRESSES tiiia r Oout...

Page 147: ...PAGE MODE READ CYCLE IHC CAS V HC J Jf w Ou1 IRAC CAS l R A CD j H RCH PAGE MODE WRITE CYCLE CAS V IHC V42...

Page 148: ...A4 A3 A2 At AO Column Add W A6 A5 A4 A3 A2 AT AO ColuTin Aria eisei Doc AG AS A4 A i A A 1 AO 12 1 1 1 1 1 5 poieniiei well filled vviih electrons Q o o 08 8 0001000 07 7 n 1 i i 05 6 110 05 5 10 1 04...

Page 149: ...GS Rating Symbol Value Unu Power Dissipation Derate Above 25 C 1 OJA 375 5 0 mw mW C DC Forward Anode Current Derate Above 25 C it 200 2 67 mA mA C DC Gate Current G 20 mA Repetitive Peak Forward Curr...

Page 150: ...Leakage Current Vs 40 Vdc T A 25 C Cathode Open Vs 40 Vdc T A 75 C Cathode Open GAO 1 0 30 5 0 75 nAdc Gate to C3 hode Leakage Current iVs 40 Vdc Anode to Cathode Shorted GKS 5 0 50 nAdc Forward Volta...

Page 151: ...Outpu 10 mA typ Power Off Source Impedance 300 Ohms mm Simple Slew Rate Control with External Capacitor Flexible Operating Supply Range e Compatible with AM Motorola MDTL and MTTL Logic Families QUAD...

Page 152: ...s occurs a low impedance to ground would exist at the power inputs to the MC1488 effectively shorting the 300 ohm output resistors to ground If all four outputs were then shorted to plus or minus 15 v...

Page 153: ...bl Input Noise Filtering QUAD SVIDTl LINE RECEIVERS RS 232C SILICON MONOLITHIC INTEGRATED CIRCUIT Utit QHV MCUBp J H 0 IP TYPICAL APPLICATION UHt RECEIVER iNTESCONhiECTlNG HC148 1 1 1 1 i TEfiCC NNEC...

Page 154: ...volts and turn off of 1 0 volt for a typical hysteresis of 250 mV The MC1489A has typical turn on of 1 95 voits and turn off of 0 8 vott for typically 1 15 volts of hysteresis Each receiver section ha...

Page 155: ...Voltages Generated by Closed Switch Purely Resistive High Isolation Resistance from Driver Short Sample and Hold Aperture Time CSg off 5 5 pF cdg off 5 5 P F o Fast Switching tdfon tr 7 ns Typical TO...

Page 156: ...ts e Compatible with MC6847 Video Displav Generator e Sound Carrier Addition Capability Modulates Channel 3 or 4 Carrier with Encoded Video Signal Low Power Dissipation e Linear Chroma Modulators for...

Page 157: ...Range Pins 5 6 7 OB 2 3 Vdc Oscillator Feedthrough Measured at Pin 8 _ 15 31 Modulation Angle 08IV7 2 0 Vdc S8IV5 2 0 Vdc l 85 100 115 Conversion Gam V8 IV7 V6h V8 IV5 V6 l 0 6 Vtp p Vdc Input Curren...

Page 158: ...H 1 II V12 6 O RF Output 5 61 7 9 3 tSV Chroma Modulator 1 Output o j a vw o v c o i V5 V6 V7 V9 F JlOk Outv Cycia Adjust FIGURE 3 TEST CIRCUIT 2 5 V 9 JT 360 2 5 6 V r 1 1 13 14 Pi T 3 579545 MH 9 M...

Page 159: ...MC1372 754...

Page 160: ...connected between this pin and dc supply Pins 13 and 14 RF Tank A tuned circuit connected between these pins deter mines the RF oscillator frequency The tuned circuit must provide a low dc resistance...

Page 161: ...le of the clock signal at pin 1 must be modified to overcome gate delays in associated equipment The duty cycle may be adjusted by varying the dc voltage applied to pin 3 This adjust ment may be made...

Page 162: ...pin represents a current source any load impedance may be selected for matching purposes and gain selection as long as the vol tage at pin 12 is high enough to prevent the output devices from reachin...

Page 163: ...Recommended Chroma Luma Signals A chroma modulation angle of 100 was chosen to facilitate a desirable selection of colors with a minimum number of input signal levels The following table demon strate...

Page 164: ...vss V L VlL vcc vcc Output Disable HiZ vss Don t Care V H vcc vcc Standby HiZ vss V H Don t Care vCc vcc Program Data tn vss Pulled VlL o v lH VlH V IHP vcc Program Verify Data out vss VlL VlL V IHP v...

Page 165: ...ge OL 2 1 mA vol 0 45 V Output High Voltage IQH 400 uA VOH 2 4 V VCC must be applied simultaneously or prior to Vpp Vcc must also be switched of simultaneously with or after Vpp With Vpp connected dir...

Page 166: ...AVQV 350 450 ns E Progr to Output Valid INote 2 ELQV 350 450 Output Enable to Output Valid E Progr V L GLQV 120 120 E Progr to Hi Z Output EHQZ 100 100 Output Disable to Hi Z Output E Progr V _ GHQZ 1...

Page 167: ...STICS Charoctonrtic Condition Symbol Mm Typ Max Unit Address G and E Progr input V in 5 25 V 0 45 Sink Current LI 10 pAdc Vpp Supply Current E Progr V 1L PPI 5 0 mAdc Vpp Programming Pulse E Progr V S...

Page 168: ...operation or may be reserved for very fast Interrupt response Each CPU also contains a 16 bit stack pointer which permits simple implementation of multiple level interrupts unlimited subroutine nestin...

Page 169: ...at the address bus holds a valid address for a memory read or memory write operation Tri state output active low The IORQ signal indicates that the lower half of the address bus holds a valid I O addr...

Page 170: ...ic memories The WR line is active when data on the data bus is stable so that it can be used directly as a R W pulse to virtually any type of semiconductor memory INPUT OR OUTPUT CYCLES Illustrated he...

Page 171: ...ss HL IX IY d any 8 bit destination register or memory location dd any 16 bit destination register or memory location e 8 bit signed 2 s complement displacement used in relative jumps and indexed addr...

Page 172: ...bolic Operation Comments a BlTb s Z Z is zero flag CC SETb s s b S 5E r HLl H RESb s s b 0 IX e lY e IN A n A n INr C r C Se t flags INI HL C HL HL 1 B B l INIR HL C HL HL I B B l Repeat until B 0 IND...

Page 173: ...k RD High RD Delay From Falling Edge ol Clock RD High 100 nsec C L S0 F 130 nsec 100 nsec 110 nsec WR DL WR1 DL WR HLl WR Delay From Rising Edge of Clock WR Law WR Delay From Falling Edge of Clock WR...

Page 174: ...A C Timing Diagram Timing measurements are made at the following voltages unless otherwise specified i 0 CLOCK Vct 6V 45V OUTPUT 0V 8 V INPUT 2 0 V 8 V FLOAT 4 V 10 5 V RESET 16...

Page 175: ...S a t Oulpui leakage Cuneni m Float 10 WA V 0lT 4 V c l 0 TriSlate Oulpui eakage Cutiem in Final 10 i A VOUT 0 4V u Data Bus Leakage iiirenl in Input Mode ilO M o v N vcc Capacitance T A 25 C f 1 MHz...

Page 176: ...c f L 50pF 95 nsec 85 nsec 85 nsec WR DL WR DL WR DH WR w WRLI WR Delav From Rising Edge of Clock WR Low WR Delav From Falling Edge of Clock WR Low WR Delay From Falling Edge uf Clock WR High Pulse Wi...

Page 177: ...xternal compensation options are available within the TL081 Family Device types with an M suffix are characterized for operation over the full military temperature range of 55 C to 125 C those with an...

Page 178: ...ifferentia voltages are at the noninvertmg input terminal with respect to The inverting input terminal 3 The magnitude of the input voltage must never exceed the magnitude of the supply voltage or 15...

Page 179: ...4 VD Large signai differential voltage amplification R L 2 kn V i10 V TA 25 C TL08_t 25 200 50 200 25 200 V mV TL08_A 50 200 81B 82B 84B 50 200 R L 2 kn V HO V Ta full range TL08_t 15 25 15 TL08_A 25...

Page 180: ...F See Figure 1 8 13 13 V mi t r Rise time V 20mV R L 2kSl C _ 100pF See Figure 1 0 1 0 1 J Overshoot factor 10 10 v Equivalent input noise voltage flS 100 1 f 1 kHz 25 25 nV x Hz PARAMETER MEASUREMENT...

Page 181: ...RE 25 HIGH Q NOTCH FILTER 1M Q VW 100 jiF T or TL085 TL084O fe f L_ 100 kfi W OVCC O OUTPUTS VCC FIGURE 26 AUDIO DISTRIBUTION AMPLIFIER 6 sm tjt 18 pF 88 4 kn 4 Vv Vcc 18 kn See Note A WV 15 V 18 pF i...

Page 182: ...16 tUl wv 16 kn vw 220 pF OUTPUT B 2 kHz div SECOND ORDER BANDPASS FILTER f 100 kHz Q 30 GAIN 4 2 kHz div CASCADED BANDPASS FILTER f 100 kHz Q 69 GAIN 16 FIGURE 28 POSITIVE FEEDBACK BANDPASS FILTER i...

Page 183: ...BY 8 BITS TOP VIEW TOP VIEW TOP VIEW TOP VIEW TOP VIEW Q0 T u 3 vcc A6 T u 3 vcc AOfT u 3vCc aoE u 3vcc A7f7 u gvoc QlH g A5fT 3A7 A1 T 5jA7 A1 7 3a8 A6 7 3A8 Q2 T 7TJA4 A4 7 3G2 A20 3a6 A2 7 1A7 A5 T...

Page 184: ...M2HXI ill A 3 A 2 3 A A Q Q aQ AO ra 141 151 mi 113 nfil A r TBP18S42 0 pnowsizxe iei 7 V 511 A 7 1 1 5 mi 1 1 1131 iiei 5 51 cat prom I 12 x a A A EN 171 19 W ioi IS1 Iltl in 13 n i 1151 11 231 1171...

Page 185: ...OUTPUTS VCC Programming circuit not shown absolute maximum ratings over operating free air temperature range unless otherwise noted Supply voltage see Note 1 Input voltage Off state output voltage Op...

Page 186: ...e of Figure 2 7 After the X pulse time is reached a high logic level is applied to the chip select inputs to disable the outputs 8 Within the range of 1 us to 1 ms after the chip select inputis reach...

Page 187: ...el input current VCC MAX V 0 5 V 250 250 uA OS Short circuit output current VqC MAX 30 100 30 100 mA ice Supply current VCC MAX Chipselectlsl st V Outputs open See Note 4 TBP14S10 100 135 100 135 mA T...

Page 188: ...0 5V 250 MA CC Supply current VcC MAX Chip select s at V Outputs open See Note 4 TBP18SA030 80 110 mA TBP14SA10 100 135 TBP18SA22 110 155 TBP18SA42 TBP18SA46 120 155 switching characteristics over re...

Page 189: ...OARD SCHEMATIC PAGE 1 OF 8 EXPANSION BOARD SCHEMATIC PAGE 2 OF 2 9 LNDOUBLER 5 8 SCHEMATICS 10 TOP ASSEMBLY LNW80 11 LNW80 PRINTED CIRCUIT BOARD COMPONENT SIDE 12 LNW80 PRINTED CIRCUIT BOARD SOLDER SI...

Page 190: ...AIN L CPU ADDRESS VIDEO ADDRESS VID AOORESS MUX LORES VID RAM VIDEO MODE SELECT U X HRES VIDEO RAM VIDEO f OC SS N VIDEO OUTPUT COLOR DATA BUS VIDEO OUTPUT B VV VlO DOT CLOCK EXPANSION INTERFACE PCB V...

Page 191: ......

Page 192: ......

Page 193: ...M _N_ 2_ UT l il i_l f_coi o 5 r c fro lOU MH KTit2 n sj io no rr 419 Z g 5 NC 12 7105 7 __T Ico aR T U CEO R LNW80 3 3 8 _ V K IS80 LNW BESEAKCM CO PO iON PASE 3 3f 4 97001...

Page 194: ...155 I S 159 1 2 1 8 l 1 70 7 Ui 8 35 5 7 73 13 84 87 88 97 01 lOJ 105 112 11 117 110 122 126 12 7 128 1 9 130 131 132 133 1 3 6 139 140 142 144 1 45 160 1 1 147 U3 4 5 17 18 32 34 53 62 83 5 S8 S9 l2...

Page 195: ...KD0 Kbl KDZ kD2 l D KDS Kb A D7 TO LAiWao J 1 80 Z gi aT LNW RESEAKCU rCKPORATlfc N i nwPO i t v BC Kb...

Page 196: ......

Page 197: ...RS2J2 RECEIVE OCE RS232 SENO OTE C34 59 L C37 39 4l r 53 55 57 6 6 old U42 49 53 60 am _ C36 38 4tt j 42 52 54 56 58 luld Ja U40 2 CE3 C44 5J 4 T loll C65 6 6 ti Id U50 tIC 15 T 6 8 T Z 12 4 CPi Jl S...

Page 198: ......

Page 199: ...zee S Pt J couuectois E z places Z PLACES in 2 PS j 111 1 r I If I D Cft 1 1 T _ _ THtk 1 l KGB O NNECTJR E CF 4 0ACES m 1 V s t OET q L A Pieces 3 rirtCES DETAIL B SCALE tJOvE LNW RESEARCH CORP V A2...

Page 200: ...COMPONENT 8I0E LNW80 pcb...

Page 201: ...SOLDER SIDE LNW80 pcb...

Page 202: ...APACITOR ZZOpp FROM UIS3 UN lZ rO CIlSS PIN 14 L tl add D capacitor lOOff ppom P140 to vro 7 I C IM 1 ADDED CA ACITOK 47f P FPOM UI38PIN9 J O 30 PlNS I C 451 I Z 7S 60 IQQ 20 Cl4t SWt SHALL BE NS iLl...

Page 203: ...w w m r w a U a a v X v v rf s jJK 1 W w U37 1 t _ v v m C i v m v tA L l ST X Il i u Ht J 9 i l _ 1 v IIMIII T v is a U H v Yr v 7 i TVi ii V f v 4 3T3fe AT H33WT3fl SvYS tOOO eV NOTES UNLESS OTHERWt...

Page 204: ...COMPONENT SIDE SYSTEM EXPANSION PCB...

Page 205: ...SYSTEM EXPANSION PCB SOLDER SIDE...

Page 206: ...wees ou sable pek table HOTf PtMEU rMMEZ TDg TD BE AfPRO 00 FFOM ED6E OF EOAZD s T WifES M r gi_E PEg T IBlE I WTE Pi 232 KB ISCEMBl TO BE APPrOX S 06 FEOM OP B0A D IEP WIPES PIAJ TO P N 4HC iECaSE J...

Page 207: ...SOLDER SIDE LNDOUBLER 5 8 PCB...

Page 208: ...ice Dept Street Address City State Zip Code Please list any discrepancy found in this manual by page paragraph figure or table number in the following space If there are any other suggestions that you...

Page 209: ...FOLD r a r r S 5 rt W f S S 9 9 B S PLACE POSTAGE HERE LNW RESEARCH CORP 2620 WALNUT TUSTIN CA AVE STE 92680 S 9 9 T9 T 3 rt S 5 fl FOLD...

Page 210: ...p m NB na n JBHHI LNW Research Cora MM WAI M 1 TuMm CA S 6 0 17 141 541 HUSO 714 544 5744 TED IN U S A...

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