Linear Technology LTC1877, Demo Manual

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DEMO MANUAL DC290
NO-DESIGN SWITCHER
REFERENCE
DESIGNATOR
QUANTITY PART NUMBER DESCRIPTION VENDOR TELEPHONE
C
FW
1 06035A200JAT 20pF 50V Chip NPO Capacitor AVX (843) 946-0362
C
ITH
1 06035A221JAT 220pF 50V Chip NPO Capacitor AVX (843) 946-0362
C1 1 06035C103MAT 0.01
µ
F 50V Chip X7R Capacitor AVX (843) 946-0362
C
IN
(LTC1877) 1 LMK325BJ106MN 10
µ
F 10V Chip X7R Capacitor TAIYO-YUDEN (408) 573-4150
C
IN
(LTC1878) 1 JMK325BJ226MM 22
µ
F 6.3V Chip X5R Capacitor TAIYO-YUDEN (408) 573-4150
C
OUT
1 6TPA47M 47
µ
F 6V POSCAP Capacitor SANYO (619) 661-6835
C
OUT1
1 LMK107F105ZA 1
µ
F 10V Chip Y5V Capacitor TAIYO-YUDEN (408) 573-4150
E1 to E7 7 2501-2 Turret, Testpoint Mill-Max (516) 922-6000
JP1, JP2 2 2802S-03-G1 0.079” Single Row Header COMM CON (626) 301-4200
JP3 1 2202S-08-G1 0.079” Double Row Header COMM CON (626) 301-4200
JP1 to JP3 3 CCIJ2MM-138G 0.079” Center Shunt COMM CON (626) 301-4200
L1 1 A920CY-100M 10
µ
H 20% Inductor TOKO (847) 699-3430
R1 1 CR16-103JM 10K 5% 1/16W Chip Resistor TAD (714) 255-9123
R3 1 CR16-8873FM 887K 1% 1/16W Chip Resistor TAD (714) 255-9123
R4 1 CR16-1004FM 1M 1% 1/16W Chip Resistor TAD (714) 255-9123
R5 1 CR16-4123FM 412K 1% 1/16W Chip Resistor TAD (800) 508-1521
R6 1 CR16-2803FM 280K 1% 1/16W Chip Resistor TAD (800) 508-1521
U1 1 LTC1877/8EMS8 Monolithic Synchronous Step-Down Regulator LTC (408) 432-1900
C2 Optional
R2, R7 Optional
PARTS LIST
Figure 2. Output Voltage Selection (JP3)
(3.3V Position Shown)
QUICK START GUIDE
JP3
3.3V 2.5V 1.5V OPEN
This demonstration board is easily set up to evaluate the
performance of the LTC1877 or LTC1878 IC. Please
follow the procedure outlined below for proper opera-
tion.
• Refer to Figure 5 for proper connection of monitoring
equipment to ensure correct measurement.
• Connect the input power supply to the V
IN
and GND
terminals on the left-hand side of the board. Do not
increase V
IN
over its rated maximum supply voltage or
the part will be damaged. For the LTC1877 the maxi-
mum V
IN
is 10V and for the LTC1878 the maximum
V
IN
is 6V.
• Connect the load between the V
OUT
and GND terminals
on the right side of the board.
• Select the desired operating mode using JP1 and JP2,
as shown in Table 1. JP1 connects SYNC/MODE to
GND in the upper position, and connects it to V
IN
in the
lower position. JP2 connects RUN to GND in the upper
position, and connects it to V
IN
in the lower position.
If a signal is applied at RUN (E1) or SYNC/MODE (E7),
then jumper JP1 or JP2, respectively, must be re-
moved.
• Set the desired output voltage with jumper JP3 as
shown in Figure 2.
Table 1. Operating Mode Selection With Jumpers JP1 and JP2
JP2 JP1 OPERATING MODE
UPPER X SHUTDOWN
LOWER UPPER PULSE SKIPPING
LOWER LOWER BURST MODE
LOWER OPEN EXTERNAL CLOCK AT SYNC/MODE
OPEN X EXTERNAL SIGNAL AT RUN