8
DEMO MANUAL DC275
DC/DC CONVERTER
OPERATIO
U
Heat Dissipation Issues
Since each side of the LTC1702 demo board can supply
15A of continuous load current, care must be taken not to
exceed the maximum junction temperature for the power
MOSFETs. A few possibilities for dissipating the power are
to use heat sinks and/or forced air cooling. Another
possibility is to use the PC board as a heat sink. On the
LTC1702 demo board, power MOSFETS Q1 to Q8 are
surrounded by ground and power planes on both sides of
the PC board. Also, there is metal on the inner layers
directly underneath the power MOSFETs. This helps in
spreading the heat and improves the power dissipation
capability of the PCB.
Layout Guidelines
Since the LTC1702 is a switching regulator, a good layout
is essential for good load regulation and minimizing radi-
ated/conducted noise. If you want a layout that is guaran-
teed to work, copy the LTC1702 Gerber files provided with
this demo board; otherwise, be sure to follow the layout
guidelines below:
1. The inductor L1, MOSFETs Q1 to Q4 and the Schottky
diode (D3) should be placed as close as possible to
each other; similarly, L2, Q5 to Q8 and D4 should be
placed as close together as possible. This junction
forms the switch node and should be kept as small as
possible to minimize radiated emissions. It must also
be large enough to carry the full rated output current.
2. The SW1 and the SW2 pins should be connected
directly to the respective switch nodes with a short
trace.
3. C4 (10
µ
F) should be as close as possible to Pin 13 on
the LTC1702.
4. C5 (1
µ
F) should be as close as possible to Pin 1 on the
LTC1702.
5. R2 should be connected directly to the sources of Q3
and Q4.
6. R10 should be connected directly to the sources of Q7
and Q8.
7. Keep the trace from the FB1 pin to the junction of R4
and R5 short and use a long trace from the top of
resistor R4 to the output terminal, rather than vice
versa.
8. Keep the trace from the FB2 pin to the junction of R12
and R13 short and use a long trace from the top of
resistor R12 to the output terminal, rather than vice
versa.
9. The sources of the bottom MOSFETs Q3, Q4, Q7 and
Q8 should be tied back to the ground of input capaci-
tors C1 to C3 by means of a wide trace, not by the
ground plane.
10. The grounds of the output capacitors C19–C20,
C25–C27 and C8–C12 should be tied directly to the
input capacitor’s ground by means of a wide trace or
by the ground plane.
11. The grounds of the feedback resistors, soft-start ca-
pacitors and C4 should be referenced to the chip SGND
pin, which is then tied to the input bulk capacitors’
grounds.
12. PGND, Pin 19, should connect directly to the ground
plane.
