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dc1925af
DEMO MANUAL DC1925A
DC1925A SETUP
DC Power
The DC1925A requires ±9VDC and draws approximately
100mA. Most of the supply current is consumed by the
CPLD, op amps, regulators and discrete logic on the board.
The +9VDC input voltage powers the ADC through LT1763
regulators which provide protection against accidental
reverse bias. Additional regulators provide power for the
CPLD and op amps. See Figure 1 for connection details.
Clock Source
You must provide a low jitter 2.5V
P-P
(if VCCIO is in the 3.3V
position, the clock amplitude should be 3.3V
P-P
) sine or
square wave to J1. The clock input is AC coupled so the DC
level of the clock signal is not important. A clock generator
like the Rohde & Schwarz SMB100A or the DC1216A-C is
recommended. Even a good clock generator can start to
produce noticeable jitter at low frequencies. Therefore it
is recommended for lower sample rates to divide down a
higher frequency clock to the desired input frequency. The
ratio of clock frequency to conversion rate is 80:1. If the
clock input is to be driven with logic, it is recommended
that the 50Ω terminator (R5) be removed. Slow rising
edges may compromise the SNR of the converter in the
presence of high amplitude higher frequency input signals.
Data Output
Parallel data output from this board (0V to 2.5V default),
if not connected to the DC890, can be acquired by a logic
analyzer, and subsequently imported into a spreadsheet, or
mathematical package depending on what form of digital
signal processing is desired. Alternatively, the data can be
fed directly into an application circuit. Use Pin 50 of P1 to
latch the data. The data can be latched using either edge
of this signal. The data output signal levels at P1 can also
be changed to 0V to 3.3V if the application circuit requires
a higher voltage. This is accomplished by moving VCCIO
(JP3) to the 3.3V position.
Reference
The default reference is a LTC6655 5V reference. If an
external reference is used it must settle quickly in the
presence of glitches on the REF pin. To use an external
reference, unsolder R37 and apply the reference voltage
to the VREF terminal.
Analog Input
The default driver for the analog inputs of the LTC2378-20
on the DC1925A is shown in Figure 2. This circuit buffers
a fully differential 0V to 5V input signal applied at AIN+
and AIN–. In addition, this circuit bandlimits the input
frequencies to approximately 1.2MHz.
Alternatively, if your application circuit requires a single-
ended signal to drive the ADC, the circuit shown in Figure 3
can be used. The circuit of Figure 3 converts a single-
ended signal to the fully-differential signal required by the
ADC. Additionally, this circuit further bandlimits the input
frequencies to 100kHz which is the bandwidth limit of the
ADC for low distortion performance.
The single-ended-to-differential circuit results in reduced
THD performance, (approximately –112dB) due to the
slight phase shift of the inverting op amp. The circuit in
Figure 3 can be implemented on the DC1925A by remov-
ing R44 and R52 and adding R57 and R58. At this point
it will only be necessary to drive AIN+ (J4).
Figure 2. Fully-Differential Driver
