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dc1717afa
DEMO MANUAL DC1717A
overview
operating principles
The LTC4417 controls three sets of external back-to-back
P-channel MOSFETs to connect the proper rail to the
load. Precision comparators are used to monitor each of
the three input rails for both UV and OV conditions. The
highest priority input supply whose voltage is within its
respective OV/UV window for at least 256ms is consid-
ered valid and connected to the load. Low signals on the
VALID1
,
VALID2
, and
VALID3
pins indicate validation of
the V1, V2, and V3 voltages.
DC1717A is designed to operate from inputs of 12V,
5V, and 8V, applied to V1, V2 and V3 respectively. The
valid range of each supply is ±20%, as set by OV and UV
comparators and their associated resistive dividers. V1
has the highest priority, V3 has the lowest. The highest
priority input that is also within its valid range is selected
to power the output. V1, V2 and V3 inputs are protected
against input glitches of up to ±42V. Maximum load cur-
rent is 2A, limited by MOSFET capability.
Logic and LEDs are included to provide visual information
about the operating status. These circuits are powered
from a 6V to 24V auxiliary voltage input (AVI) which is
regulated by an LT3060 (U4) to 5V. This auxiliary 5V rail
also powers 100kΩ pull-ups for
VALID
pins. AVI must be
present in order for the board to operate. See the Modifica-
tion section for a means of eliminating AVI.
To eliminate back-and-forth switching during rail switcho-
ver, the LTC4417 provides a 30mV hysteresis in the OV and
UV comparators, and an externally adjustable current mode
hysteresis using the OV/UV resistive dividers. DC1717A’s
input reference hysteresis is 6%, and can be changed to
3% by moving the JP1 jumper to the 30mV position.
The controller’s “break-before-make” switching method
prevents cross conduction between input channels and
reverse current from the output capacitor into the selected
input supply.
Each channel’s control circuit of the LTC4417 has a REV
comparator, which monitors the connecting input supply
and output load voltage. The REV comparator delays the
connection until the output voltage droops 120mV below
the input voltage. This prevents reverse current.
The LTC4417 has two common control pins: EN and
SHDN
.
Pulling the EN pin below 1V turns off all external back-to-
back P-channel MOSFETs. When this pin is driven above
1V, the highest priority valid channel is connected to the
load. All these actions are provided without resetting the
256ms OV/UV timers.
Pulling the
SHDN
pin below 0.8V turns off all external
back-to-back P-channel MOSFETs, placing the controller
in a low current state and resetting the 256ms timers
used to validate input rail voltages. It requires at least
256ms to validate each rail voltage after the
SHDN
pin
signal goes high.
The LTC4417 features two different driving modes for the
P-channel MOSFET gates.
One mode is provided by the internal soft-start circuitry,
which limits output voltage slew rate to no more than
5V/ms. As the highest output voltage slew rate, usually, can
impose the highest requirements for circuit components,
5V/ms should be taken into account as a worst case for
component selection.
The soft-start circuitry is enabled each time under the
following conditions:
•
If the LTC4417 is first powered on, or
•
If
SHDN
is forced low, or
•
If V
OUT
falls below ~0.7V
Soft-start is disabled when:
•
any channel turns off, including the channel that is soft
starting.
• 32
ms validation delay time has elapsed during the soft-
start interval.
