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dc1843bfa

DEMO MANUAL DC1843B

DEMONSTRATION CIRCUIT 1842B LAYOUT

Layer 4: Bottom Layer

Bottom Assembly

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Summary of Contents for DC1680B

Page 1: ...manual provides a Quick Start Procedure a DC1842B overview a DC1680B overview schematics and layout printouts Refer to the Layout Guide for Demonstration Circuit 1842B when L LT LTC LTM Linear Technology and the Linear logo are registered trademarks and QuikEval is a trademark of Linear Technology Corporation All other trademarks are the property of their respective owners BOARD PHOTO laying out t...

Page 2: ... jumper JP1 to HI Figure 1 to enable AUTO pin mode 2 On the DC1842B set MID jumper JP2 to LO Figure 1 to disable midspan mode 3 Alignpin1ofthe30 pinmaleconnectorontheDC1842B with pin 1 of the 30 pin female connector on the DC1680B Figure2 Pin12ispolarizedtoassistwiththe alignment Carefully push the DC1842B straight down untilthetwo30 pinconnectorsareflushwitheachother 4 On the DC1680B connect a su...

Page 3: ...3 dc1843bfa DEMO MANUAL DC1843B QUICK START PROCEDURE Figure 3 DC1843B Basic Setup Figure 4 DC1843 System Setup with the DC590 DC1680 DC1842 and 51V to 57V Power Supply ...

Page 4: ...ed power management features in the LTC4290B LTC4271 chipset include per port 12 bit current monitor ing ADCs DAC programmable current limit and versatile quick shutdown of preselected ports PD discovery uses a proprietarydualmode4 pointdetectionmechanismensur ing excellent immunity from false PD detection Midspan PSEs are supported with 2 event classification and a two second backoff timer The LT...

Page 5: ...ides communication across an isolation barrier through a data transformer Figure 6 This eliminates the need for expensive opto couplers All digital pins reside on the digital ground refer ence and are isolated from the analog PoE supply A 3 3V supply for VDD and an isolated VEE supply are connected to the DC1842B through the 30 pin connector VDD33 VDD33 T1 DND CPD CND DPD AGND VEE DNA VEE VEE ISOL...

Page 6: ... the states of the LTC4290B LTC4271 chipset general purpose input outputpins Thesepinsareconfiguredasinputsoroutputs via I2C GP1 and GP0 are referenced to DGND and driven by the LTC4271 when set as outputs Figure 8 XIO0 and XIO1arereferencedtoVEE andaredrivenbytheLTC4290B when set as outputs Figure 9 J2 provides test points for access to these I Os Figure 8 DC1842B LTC4290B General Purpose I O LED...

Page 7: ...n be subject to significant cable surge events TokeepPoEvoltagesbelowasafelevelandprotect the application against damage protection components as shown in Figure 11 are required at the main supply at the LTC4270 supply pins and at each port Bulk transient voltage suppression TVSBULK and bulk capacitance CBULK are required across the main PoE supply and should be sized to accommodate system level s...

Page 8: ...re 3 Test points for port outputs OUT1 through OUT8 are provided 8 Port Configuration TheDC1680Bisconfiguredforan8 portPSEmotherboard for the DC1843B kit Four RJ45 dust caps at J3 and four dust caps at J4 are inserted to block off the four unused Ethernet ports Additional pegs are placed in the last 4 pins of connector J1 to block off the unused pins when the DC1842B daughter card is inserted DC16...

Page 9: ...enheldinactivewithallportsoffandallinternalregisters reset to their power up states When SW1 is released RESETispulledhigh andthePSEbeginsnormaloperation PushbuttonswitchSW2whenpressedpullsthemaskable shutdown input MSD pin of the daughter card logic low Whenpressed allportsthathavetheircorrespondingmask bit set in the mconfig register of the PSE controller will be shutdown These ports must then b...

Page 10: ...EDs Interrupt LED A red LED indicates when the INT line is pulled logic low by the daughter card When the interrupt is cleared high via I2C servicing the LED is turned off Port 1 Through 8 Power LED Indicators Each PSE port has a green LED indicator to show when PoE power is present at the port The LEDs are driven by the respective port OUT voltage ...

Page 11: ... A power supply is connectedtoVEEwithbananacables TheDC590connects with a 14 pin ribbon cable to the DC1680B and to a PC via USB On the PC a GUI communicates with the board At the PSE output PDs are connected A sample PD demo board is shown in Figure 14 Table 2 DC1843 Kit Versions VERSION FEATURES DC1843A DC1680A Motherboard with Integrated Magjack DC1842A 8 Port PSE Daughter Card DC1843B DC1680B ...

Page 12: ...12 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1842B LAYOUT Top Assembly Layer 1 Top Layer ...

Page 13: ...13 dc1843bfa DEMO MANUAL DC1843B Layer 2 VEE Plane 1 DEMONSTRATION CIRCUIT 1842B LAYOUT Layer 3 VEE Plane 2 ...

Page 14: ...14 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1842B LAYOUT Layer 4 Bottom Layer Bottom Assembly ...

Page 15: ...15 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Top Assembly ...

Page 16: ...16 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Layer 1 Top Layer ...

Page 17: ...17 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Layer 2 AGND CGND Plane 1 ...

Page 18: ...18 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Layer 3 SIG AGND CGND Plane 2 ...

Page 19: ...19 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Layer 4 SIG AGND CGND Plane 3 ...

Page 20: ...20 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Layer 5 SIG AGND CGND Plane 4 ...

Page 21: ...21 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Layer 6 Bottom Layer ...

Page 22: ...22 dc1843bfa DEMO MANUAL DC1843B DEMONSTRATION CIRCUIT 1680B LAYOUT Bottom Assembly ...

Page 23: ...RELIABLE OPERATION IN THE ACTUAL APPLICATION COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE THIS CIRCUIT IS PROPRIETARY TO LINEAR TECHNOLOGY AND SCHEMATIC SUPPLIED FOR USE WITH LINEAR TECHNOLOGY PARTS SCALE NONE www linear com 1 1 1 8 PORT PSE DAUGHTER CARD WITH DI...

Page 24: ... SHEET OF TITLE APPROVALS PCB DES APP ENG TECHNOLOGY Fax 408 434 0507 Milpitas CA 95035 Phone 408 432 1900 1630 McCarthy Blvd LTC Confidential For Customer Use Only CUSTOMER NOTICE LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER SUPPLIED SPECIFICATIONS HOWEVER IT REMAINS THE CUSTOMER S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION...

Page 25: ...A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER SUPPLIED SPECIFICATIONS HOWEVER IT REMAINS THE CUSTOMER S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY CONTACT LINEAR TECHNOLOGY APPLICATIONS ENGINEERING FOR ASSISTANCE THIS CIRCUIT IS PROPRIETA...

Page 26: ... LTC Confidential For Customer Use Only CUSTOMER NOTICE LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER SUPPLIED SPECIFICATIONS HOWEVER IT REMAINS THE CUSTOMER S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATION COMPONENT SUBSTITUTION AND PRINTED CIRCUIT BOARD LAYOUT MAY SIGNIFICANTLY AFFECT CIRCUIT PERFORMANCE OR RELIABILITY CONTACT ...

Page 27: ...V SHEET OF TITLE APPROVALS PCB DES APP ENG TECHNOLOGY Fax 408 434 0507 Milpitas CA 95035 Phone 408 432 1900 1630 McCarthy Blvd LTC Confidential For Customer Use Only CUSTOMER NOTICE LINEAR TECHNOLOGY HAS MADE A BEST EFFORT TO DESIGN A CIRCUIT THAT MEETS CUSTOMER SUPPLIED SPECIFICATIONS HOWEVER IT REMAINS THE CUSTOMER S RESPONSIBILITY TO VERIFY PROPER AND RELIABLE OPERATION IN THE ACTUAL APPLICATIO...

Page 28: ...INCLUDING ANY WARRANTY OF MERCHANTABILITY OR FITNESS FOR ANY PARTICULAR PURPOSE EXCEPT TO THE EXTENT OF THIS INDEMNITY NEITHER PARTY SHALL BE LIABLE TO THE OTHER FOR ANY INDIRECT SPECIAL INCIDENTAL OR CONSEQUENTIAL DAMAGES The user assumes all responsibility and liability for proper and safe handling of the goods Further the user releases LTC from all claims arising from the handling or use of the...

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