2
dc1624af
DEMO MANUAL DC1624A
perForMAnce sUMMArY
qUick stArt proceDUre
The LTC4225 functions as an ideal diode with inrush cur-
rent limiting and overcurrent protection by controlling
two external back-to-back N-channel MOSFETs in a power
path. The LTC4225 has two ideal diode and two Hot Swap
controllers. Each ideal diode MOSFET is intended to oper-
ate with a defined Hot Swap MOSFET, because they are
tied by common on/off control, and ideal diode controller
sense voltage includes both MOSFETs and sense resistor
voltage drop. Therefore, LTC4225 provides independent
control for the two input supplies.
The LTC4225 gate drive amplifiers (DGATE
N
,) monitor
the voltage between the IN
N
and OUT
N
pins and drive the
DGATE
N
pins. The amplifier quickly pulls up the DGATE
pin, turning on the MOSFET (Q1 or Q3), for ideal diode
control when it senses a large forward voltage drop.
Pulling the ON pin high and
EN
pins low initiates a 100ms
debounce timing cycle. After 100ms, a 10µA current source
from the charge pump ramps up the HGATE
N
pin. When
the Hot Swap MOSFET (Q2 or Q4) turns on, the inrush
current is limited to a set level set by an external sense
resistor placed between IN and SENSE pins.
SYMBOL
PARAMETER
CONDITIONS
MIN
TYP
MAX
UNITS
I
HGATE(UP)
External N-Channel Gate Pull-Up Current
Gate Drive On, HGATE = 0V
7
10
13
µA
I
HGATE(DN)
External N-Channel Gate Pull-Down Current
Gate Drive Off, OUT = 12V, HGATE = OUT + 5V
150
300
500
µA
I
HGATE(FPD)
External N-Channel Gate Fast Pull-Down
Current
Fast Turn-Off, OUT = 12V, HGATE = OUT + 5V
100
200
300
mA
Input/Output Pin
V
ON(TH)
ON
N
On Pin Threshold Voltage
ON Rising
1.21
1.235
1.26
V
V
ON(RESET)
ON
N
Pin Fault Reset Threshold Voltage
ON Falling
0.55
0.6
0.63
V
V
EN
(TH)
EN
N
Pin Threshold Voltage
EN
Rising
1.185
1.235
1.284
V
V
TMR(TH)
TMR
N
Pin Threshold Voltage
TMR Rising
TMR Falling
1.198
0.15
1.235
0.2
1.272
0.25
V
V
I
TMR(UP)
TMR
N
Pin Pull-Up Current
TMR = 1V, In Fault Mode
75
100
125
µA
I
TMR(DN)
TMR
N
Pin Pull-Down Current
TMR = 2V, No Faults
1.4
2
2.6
µA
I
TMR(RATIO)
TMR
N
Current Ratio I
TMR(DN)/
I
TMR(UP)
1.4
2
2.7
%
(T
A
= 25°C)
An active current limit amplifier servos the gate of the
MOSFET to 65mV across the current sense resistor. In-
rush current can be further reduced, if desired, by adding
a capacitor from HGATE to GND. When the MOSFET’s
gate overdrive (HGATE to OUT voltage) exceeds 4.2V, the
PWRGD
pin pulls low.
When both MOSFETs (Q1 and Q2 or Q3 and Q4) are turned
on, the gate drive amplifier controls DGATE to servo the
forward voltage drop (V
IN
-
V
OUT
) across the sense resistor
and the back-to-back MOSFETs to 25mV. If the load current
causes more than 25mV of voltage drop, the gate voltage
rises to enhance the MOSFET used for ideal diode control.
For large output currents the MOSFET’s gate is driven
fully on and the voltage drop is equal to the sum of the
I
LOAD
• RD
S(ON
) of the two MOSFETs in series.
In the case of an input supply short circuit when the
MOSFETs are conducting, a large reverse current starts
flowing from the load towards the input. The gate drive
amplifier detects this failure condition as soon as it ap-
pears and turns off the ideal diode MOSFET by pulling
down the DGATE pin.
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