4
dc1814afe
DEMO MANUAL
DC1814A
Figure 4. DC1814A LDO Circuit for the LTC4274A Digital Supply
U1
LTC4274AIUHF
AGND
VEE
VEE
VEE
VEE
VEE
VEE
VDD
VEE
C1
0.1µF
D23
5.6V
R5
100k
Q2
CMPTA92
DGND
R10
1Ω
DGND
DGND
DGND
DGND
13
10
15
16
17
DC1814A F04
18
22
19
25 26 27 39
D1
3.8V
MMSZ4686T1
R11
1k
1/4W
suppLy VoLtages
Select a VEE supply with enough power to sustain the port
at maximum load. Table 1 shows the maximum delivered
PD power as well as a recommended VEE power supply
minimum to avoid drooping in a worst case scenario with
I
LIM
current.
The LTC4274A also requires a digital 3.3V supply. The
DC1814A uses a simple LDO regulator circuit to power the
3.3V digital supply from the VEE supply. The LTC4274A VDD
supply is allowed to be within 5V above or below AGND. On
the DC1814A, VDD is tied to AGND and DGND is a negative
voltage below AGND. D1, R5, Q2, and R11 generate the
negative voltage referenced to AGND (Figure 4). These
components are sized to handle the power required to
supply the LTC4274A and LEDs on the DC1814A. Contact
Linear Technology Applications for 3.3V options.
Surge Protection
Ethernet ports can be subject to significant cable surge
events. To keep PoE voltages below a safe level and protect
the application against damage, protection components
are required at the main supply, at the LTC4274A supply
pins and at the port. Refer to Figure 5.
Bulk transient voltage suppression devices and bulk
capacitance are required across the main PoE supply
and should be sized to accommodate system level surge
requirements. Across the LTC4274A AGND pin and VEE
pin are an SMAJ58A, 58V TVS and a 1μF, 100V bypass
capacitor. These components must be placed close to the
LTC4274A pins.
In a high surge environment, a 10Ω, 0805 resistor in series
from supply AGND to the LTC4274A AGND and VDD pin is
recommended. The bulk TVS and capacitance remain on
the supply side of this 10Ω resistor. The LTC4274A supply
pins local TVS and capacitance remain at the LTC4274A
side of this 10Ω resistor.
The port requires a pair of S1B clamp diodes: one from
OUT to supply AGND and one from supply VEE to OUT. The
diodes at the ports steer harmful surges into the supply
rails where they are absorbed by the surge suppressors
and the VEE bypass capacitance. The layout of these paths
must be low impedance.
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