LG TCH-800, Service Manual

Page: 22 / 36

- 2-18 -
PIN DESCRIPTION (continued)
Pin No. Symbol I/O Description
36 MLT I Latch Signal input from Micom(Schmit Trigger)
37 MDAT I Serial data input from Micom(Schmit Trigger)
38 MCK I Serial clock input from Micom(Schmit Trigger)
39 DB8 I/O SRAM data I/O port8(MSB)
40 DB7 I/O SRAM data I/O port7
41 DB6 I/O SRAM data I/O port6
42 DB5 I/O SRAM data I/O port5
43 DB4 I/O SRAM data I/O port4
44 DB3 I/O SRAM data I/O port3
45 DB2 I/O SRAM data I/O port2
46 DB1 I/O SRAM data I/O port1(LSB)
47 C1F1 I/O Monitoring output for C1 error correction(RA1)
48 C1F2 I/O Monitoring output for C1 error correction(RA2)
49 C2F1 I/O Monitoring output for C2 error correction(RA3)
50 C2F2 I/O Monitoring output for C2 error correction(RA4)
51 C2FL I/O C2 decoder flag(RA5, “H”:When the processing C2 code is impossible correction status)
52 /PBCK I/O Output of VCO/2 (4.3218MHz) (RA6)
53 DVSS2 I/O Digital ground 2
54 FSDW I/O Window or unprotected frame sync(RA7)
55 ULKFS I/O Frame sync protection state(RA8)
56 /JIT I/O Display of either RAM overflow or underflow for ± 4 frame jitter margin(RA9)
57 C4M I/O Only monitoring signal(4.2336MHz) (RA10)
58 C16M I/O 16.9344MHz signal output (RA11)
59 /WE I/O Terminal for test
60 /CS I/O Terminal for test
61 XTALSEL I Mode Selection 1(H:33.8688MHz, L:16.9344MHz)
62 TEST0 I TEST input terminal(GND connection)
63 CDROM I Mode Selection2 (H:CDROM, L:CDP)
64 SRAM I TEST input terminal(GND connection)
65 TEST1 I TEST input terminal(GND connection)
66 EFMI I EFM signal input
67 ADATAI I Serial audio data input of 48 bit/Slot(MSB first)
68 /ISTAT O The internal status output
69 TRCNT I Tracking counter input signal