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Copyright ©
LG Electronics Inc. All rights reserved.
Only for training and service purposes.
BLOCK DIAGRAM
OCP 1.5A
Audio
2
AM
P
Main IC
USB1
(2.0
)
OPTIC
LA
N
DDR4
(512MB X 2EA)
HDMI1
(2.0
)
HDMI2
(2.0
)
HDMI3 (2.0
)
SYSTEM
EEPROM
USB2
(2.0)
USB3
(2.0)
eMMC
Mico
m
P_TS
X_TA
L
I2S Ou
t
R E A R
S I D E
R E A R (H)
SPDIF
OU
T
BLUTOOTH
IR/KEY/EYE
WIFI
SU
B
ASSY
IR
KE
Y
I2C
CVBS/SIF
Tune
r
(ARC)
X_TA
L
OCP 1.5A
OCP 1.5A
HDMI4 (2.0
)
DDR
Controller
DDR4
(512MB X 2EA)
DDR4
(512MB X 2EA)
RS232C
RS232C
Cont
ro
l
AV/CVB
S
AV/CVB
S
1. Main
Summary of Contents for OLED65E8PUA
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